A pipelined architecture for real time correction of non-uniformity in infrared focal plane arrays imaging system using multiprocessors

Zou, Liyong; Fu, Zhuang; Zhao, Yanzheng; Yang, Junyan

doi:10.1016/j.infrared.2010.03.001

Cited by 7 publications

(2 citation statements)

References 32 publications

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“…The system processed video frames of 284 Â 288 14-bit pixels on line, and could achieve a maximum frequency of 68:1 MHz, more than ten times the 6:25 MHz required by the design. Zou also implemented a reference-based NUC using a pipelined architecture on an Altera NIOS II FPGA, and used an external DSP for image processing and pattern recognition [23]. This system also used the embedded processors on the FPGA to update NUC parameters during calibration, and to control data and external memory transactions.…”

Section: Related Workmentioning

confidence: 99%

Embedded nonuniformity correction in infrared focal plane arrays using the Constant Range algorithm

Redlich

Figueroa

Torres

et al. 2015

Infrared Physics & Technology

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Section: Related Workmentioning

confidence: 99%

Embedded nonuniformity correction in infrared focal plane arrays using the Constant Range algorithm

Redlich

Figueroa

Torres

et al. 2015

Infrared Physics & Technology

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“…Because the FPGA-based systems combine the advantages of digital signal processors (DSPs) and Application Specific Integrated Circuits (ASICs), they include shorter design time, reusability, low cost, less human resource requirements, increasing system safety and they are easy to upgrade [14][15]; the soft-processor is the inherent flexibility that allows specialization to an application through configuration and provides access beyond the actual FPGA chip through integrated standard or custom interfaces [16]. In this work, the output signals of CCD were processed by a series of pre-processing circuits and A/D chip, then the signal was collected by the FPGA board with the core of an embedded Nios II software processor and transferred to a host computer [17]. There were two software parts for the detection system.…”

Section: Introductionmentioning

confidence: 99%

Signal Detection of Multi-Channel Capillary Electrophoresis Chip Based on CCD

Lv¹,

Wang

Yang³

et al. 2012

Measurement Science Review

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A kind of multi-channel capillary electrophoresis (CE) chip signal detection system based on CCD was developed. The output signal of the CCD sensor was processed by a series of pre-processing circuits and ADC, and then it was collected by the Field Programmable Gate Array (FPGA) chip which communicated with a host computer. The core in FPGA was designed to control the signal flow of the CCD and transfer the data to PC based on a Nios II embedded soft-processor. The application of PC was used to store the data and demonstrate the curve. The measurement of the fluorescent signals for different concentration Rhodamine B dyes is presented and the comparison with other detection systems is also discussed.

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Flexible VLIW processor based on FPGA for efficient embedded real-time image processing

Brost

Yang

Meunier

2013

J Real-Time Image Proc

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International audienceModern FPGA (Field Programmable Gate Array) chips, with their larger memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high density FPGAs it is now possible to implement a high performance VLIW (Very Long Instruction Word) processor core in an FPGA. With VLIW architecture, the processor effectiveness depends on the ability of compilers to provide sufficient ILP (Instruction Level Parallelism) from program code. This paper describes research result about enabling the VLIW processor model for real-time processing applications by exploiting FPGA technology. Our goals are to keep the flexibility of processors in order to shorten the development cycle, and to use the powerful FPGA resources in order to increase real-time performance. We present a flexible VLIW VHDL processor model with a variable instruction set and a customizable architecture which allow exploiting intrinsic parallelism of a target application using advanced compiler technology and implementing it in an optimal manner on FPGA. Some common algorithms of image processing were tested and validated using the proposed development cycle. We also realized the rapid prototyping of embedded contactless palmprint extraction on an FPGA Virtex-6 based board for a biometric application and obtained a processing time of 145.6 ms per image. Our approach applies some criteria for co-design tools: flexibility, modularity, performance, and reusability

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A pipelined architecture for real time correction of non-uniformity in infrared focal plane arrays imaging system using multiprocessors

Cited by 7 publications

References 32 publications

Embedded nonuniformity correction in infrared focal plane arrays using the Constant Range algorithm

Embedded nonuniformity correction in infrared focal plane arrays using the Constant Range algorithm

Signal Detection of Multi-Channel Capillary Electrophoresis Chip Based on CCD

Flexible VLIW processor based on FPGA for efficient embedded real-time image processing

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