A Pipelined Memristive Neural Network Analog-to-Digital Converter

Abstract

With the advent of high-speed, high-precision, and low-power mixed-signal systems, there is an ever-growing demand for accurate, fast, and energy-efficient analog-to-digital (ADCs) and digital-to-analog converters (DACs). Unfortunately, with the downscaling of CMOS technology, modern ADCs trade off speed, power and accuracy. Recently, memristive neuromorphic architectures of four-bit ADC/DAC have been proposed. Such converters can be trained in real-time using machine learning algorithms, to break through the speedpower-accuracy trade-off while optimizing the conversion performance for different applications. However, scaling such architectures above four bits is challenging. This paper proposes a scalable and modular neural network ADC architecture based on a pipeline of four-bit converters, preserving their inherent advantages in application reconfiguration, mismatch selfcalibration, noise tolerance, and power optimization, while approaching higher resolution and throughput in penalty of latency. SPICE evaluation shows that an 8-bit pipelined ADC achieves 0.18 LSB INL, 0.20 LSB DNL, 7.6 ENOB, and 0.97 fJ/conv FOM. This work presents a significant step towards the realization of large-scale neuromorphic data converters.

Pipelined Memristive neural network analog-to-digital converter

“…Because of the particularity of the structure of Memristor neural network ADC, the output needs to be fed back into the synaptic array, so that the neural network can maintain the stability of the energy function, so that the results of Memristor neural network ADC quantification can remain stable. Therefore, in [2], the 8-bit pipeline architecture [2] is: the first level Memristor neural network ADC sub level uses continuous input, the output stage samples, and the output digital code is stable by using D flip-flop to latch. Since the Memristor neural network ADC always has unstable output, when sampling the output, the sampling results still have error code.…”

“…Therefore, this paper illustrates the influence of unstable output of Memristor neural network ADC on dynamic performance through simulation. In Figure 3 based on the pipeline architecture proposed by [2], the output of the first stage is simulated. Based on Simulink, a 4-bit Memristor neural network ADC sub stage is built, in which the input signal of Memristor neural network ADC is a continuous analog signal Vin, and the output signal is a digital code D7D6D5D4.…”

“…And Vh2 is the analog voltage obtained after sampling Vh1 by the sampling circuit. Due to the sampling frequency of 1.66 GHz, the bandwidth of the operational amplifier needs to be higher than this frequency, set to 4 GHz, and the sampling rate and operational amplifier bandwidth should be consistent with [2].…”

“…This article takes the input signal Vin=0.5 V as an example to analyze its conversion principle. When the input signal Vin changes from 0.499V to 0.5001V, according to the definition formula of the highest output bit D7 of the Memristor neural network ADC, it can be seen that: Therefore, based on the Danish [2] architecture, this section evaluates the dynamic performance of the first level 4 bit Memristor neural network ADC through the ADC AC Measurement module.…”

“…Therefore, this chapter designs an 8-bit Memristor neural network ADC with pipeline architecture. First, the pipeline architecture cascades 4 bit sub stages to improve the effective conversion accuracy of memristor neural network ADC [2] . Without changing the architecture of the Memristor neural network ADC sub level, the sampling speed can be improved by increasing the bandwidth of the operational amplifier.…”