A pipelined VLSI architecture for Sample Adaptive Offset (SAO) filter and deblocking filter of HEVC

Abstract

This paper present a high throughput design for Sample Adaptive offset (SAO) filter and deblocking filter used in an HEVC decoder. A five-stage pipelined architecture is proposed to support both SAO filter and deblocking filter on a 32 × 32 pixel block basis. Deblocking filter and SAO filter can work simultaneously in consecutive pipeline stages. The on-chip SRAM can also be shared by deblocking filter and SAO filter. Coupled with the novel filter order, an interlaced SRAM memory mapping scheme is proposed to increase the throughput for deblocking filter. The experimental results show that our design can support 4K × 2K@60 fps (4096 × 2304) HEVC video sequence at the working frequency of only 60.8 MHz.

Five-stage pipelined dual-edge deblocking filter architecture for H.265 video codec

“…In few architectures, the novel filter ordering is proposed to improve the performance. Different architectures are implemented in [5,7,8,9,10,11,12,13,14] to realize the deblocking filter of H.265 coding standard in hardware. It is seen that the complexity of H.265 deblocking filter architecture is less compared to the H.264 deblocking filter architecture [15].…”

“…It is seen that the complexity of H.265 deblocking filter architecture is less compared to the H.264 deblocking filter architecture [15]. Combined deblocking and SAO filter are implemented in [8,14,16,17,18]. In [13,19] the in-loop filtering is implemented in parallel fashion on graphics processing unit (GPU).…”