A Placement-Aware Soft Error Rate Estimation of Combinational Circuits for Multiple Transient Faults in CMOS Technology

SET Pulse Characterization and SER Estimation in Combinational Logic with Placement and Multiple Transient Faults Considerations

“…Nevertheless, if only logic-level netlists are used for the determination of circuits' error sites, neglecting the layout-level adjacency of the cells, may result in inaccurate estimation. Finally, other approaches provide a more realistic and reliable SER estimation analysis, by taking into consideration the circuit layout [26,27,[30][31][32][33].…”

“…The DEF (Design Exchange Format) files are parsed -for the corresponding ISCAS' 89 benchmark circuits -which describe the position and placement orientation of each logic cell on the circuit layout. For the identification of the sensitive zones on the circuit layout the GDSII (Graphic Data System) file of each cell was used [30]. These files contain ICs layout information, hence a parser is incorporated into the proposed tool for the extraction of the precise location of the transistor diffusions, and as a result the sensitive regions on the die area.…”

“…These files contain ICs layout information, hence a parser is incorporated into the proposed tool for the extraction of the precise location of the transistor diffusions, and as a result the sensitive regions on the die area. This is a crucial process, since affected cells from a particle strike are considered those whose inactive transistors are located within the oval area [26,30,31].…”

“…In order to identify circuit vulnerability to TFs, a topological analysis is presented, based on the division of the circuit layout to several smaller equal parts, called henceforth grids [30]. The number of grids may differ depending on the intended level of granularity.…”

Models and algorithms of soft error inducing mechanisms in ICs

“…Though none of the aforementioned works take into consideration this trend, a number of research studies on the evaluation of SER, considering Single Event Multiple Transients (SEMT), have emerged recently. Generally, there are two types of approaches that predominate in the literature: (i) the non-layout-aware [52,53,54] and (ii) the layout-aware [55,56,57,58,59,60,61]. The former works consider that SEMTs occur at the output of the physically adjacent gates, which are identified at the gate-level by examining fan-outs and fan-ins.…”