A platform for multi reconfigurable instruction set processor system on chip (MRPSoC)

Abstract

The rapid growth of computation requirements has caused traditional platforms to become deficient in providing the desired conditions of evolving applications. Multiprocessor system on chip (MPSoC) and application specific instruction set (ASIP) are two interesting solutions that can be employed to attain optimal throughput. This paper describes a novel platform for MPSoC adapting processing elements to specific application by means of reconfigurable hardware. The proposed platform consists of multi reconfigurable instruction set processors System on Chip (MRPSoC). The platform can run applications in parallel and enhance performance due to its reconfigurable function unit (RFU), while retaining programmability. Also, we introduce a methodology along with MRPSoC to efficiently use the platform. In MRPSoC, custom instructions (CIs) of critical portions of the code are executed on RFU. To verify the efficiency of our platform, we run applications such as multimedia, networking and encryption. Finally, we show that the completion time of applications is improved by 40.90% on average compared to homogeneous MPSoCs.

Performance Enhancement Technique in Multiprocessors

“…A survey of three papers giving details of techniques used to meet some of the objectives of this work is given below, [1] To address the issues of parallelism, a parallel programming methodology is proposed in this paper, which utilizes the multigrain parallelism in CMP, for multimedia application. However, hardware must fully exploit the parallelism, at the same time programmer should explicitly parallel programme the tasks.…”