A Platform to Analyze DDR3 DRAM’s Power and Retention Time

Jung, Matthias; Mathew, Deepak M.; Rheinländer, Carl C.; Weis, Christian; Wehn, Norbert

doi:10.1109/mdat.2017.2705144

Cited by 30 publications

(28 citation statements)

References 11 publications

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“…For example, several previous studies have proposed fine-grained methods to control DRAM parameters based on the retention time measured for each cell [40], [62]. To measure the retention time, authors use micro-benchmarks that implement the worst-case data pattern manifesting errors in the vast majority of error-prone memory locations [3], [19], [22], [27]. However, our study shows that real applications may trigger errors in many more memory locations than the conventional data pattern microbenchmarks.…”

Section: Dram Error Behavior: Workload-dependent Parametersmentioning

confidence: 99%

“…DRAM Thermal Testbed on a Server. To perform the experiments under controlled temperatures, we implement a temperature-controlled testbed using heating elements [22] for DRAMs on a server. Figure 5 shows the X-Gene2 board with four DIMMs fitted with our custom adapters.…”

Section: A Experimental Frameworkmentioning

confidence: 99%

“…Moreover, the vast majority of research studies have considered only hardware-level techniques to mitigate errors for DRAM operating under scaled [3], [19], [22], [62], which introduce additional power and chip area overheads. However, as we see, even compiler optimizations may implicitly affect DRAM error behavior.…”

Section: Workload-aware Modeling Vs Conventional Modelingmentioning

confidence: 99%

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Workload-Aware DRAM Error Prediction using Machine Learning

Mukhanov

Tovletoglou

Vandierendonck

et al. 2019

2019 IEEE International Symposium on Workload Characterization (IISWC)

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The aggressive scaling of technology may have helped to meet the growing demand for higher memory capacity and density, but has also made DRAM cells more prone to errors. Such a reality triggered a lot of interest in modeling DRAM behavior for either predicting the errors in advance or for adjusting DRAM circuit parameters to achieve a better tradeoff between energy efficiency and reliability. Existing modeling efforts may have studied the impact of few operating parameters and temperature on DRAM reliability using custom FPGAs setups, however they neglected the combined effect of workloadspecific features that can be systematically investigated only on a real system.In this paper, we present the results of our study on workloaddependent DRAM error behavior within a real server considering various operating parameters, such as the refresh rate, voltage and temperature. We show that the rate of single-and multi-bit errors may vary across workloads by 8x, indicating that program inherent features can affect DRAM reliability significantly. Based on this observation, we extract 249 features, such as the memory access rate, the rate of cache misses, the memory reuse time and data entropy, from various compute-intensive, caching and analytics benchmarks. We apply several supervised learning methods to construct the DRAM error behavior model for 72 servergrade DRAM chips using the memory operating parameters and extracted program inherent features. Our results show that, with an appropriate choice of program features and supervised learning method, the rate of single-and multi-bit errors can be predicted for a specific DRAM module with an average error of less than 10.5 %, as opposed to the 2.9x estimation error obtained for a conventional workload-unaware error model. Our model enables designers to predict DRAM errors in advance for less than a second and study the impact of any workload and applied software optimizations on DRAM reliability.

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Section: Dram Error Behavior: Workload-dependent Parametersmentioning

confidence: 99%

Section: A Experimental Frameworkmentioning

confidence: 99%

Section: Workload-aware Modeling Vs Conventional Modelingmentioning

confidence: 99%

See 1 more Smart Citation

Workload-Aware DRAM Error Prediction using Machine Learning

Mukhanov

Tovletoglou

Vandierendonck

et al. 2019

2019 IEEE International Symposium on Workload Characterization (IISWC)

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“…Conventionally, all DDR technologies adopt today a refresh period, TREF P , of 64 ms for refreshing periodically each cell of the DIMM based on the worst case retention time across all cells. However, in reality many cells have a much higher retention time and the operating conditions may not be as bad as the ones assumed [12], [14]. It was shown that such a pessimistic TREF P leads to considerable power and performance overheads, which are expected to worsen as the DRAM density increases [10].…”

Section: Dram Background and Challengesmentioning

confidence: 99%

“…However, it is questionable if the conventionally used data patterns will be effective for characterizing the DRAMs within servers in the field, where any thermal testbed (commonly used to stress the DRAM temperature in existing studies) will be unavailable. Furthermore, existing characterization campaigns were performed on FPGAs under fixed DRAM temperatures [9], [10], [11], [12], not allowing them to study any dynamic system level effects which may be excited by any executed application within a server and directly or indirectly affect DRAM reliability. Such an impact on DRAM reliability, caused indirectly by the system utilization, was also suspected in a long term study in a Google data center [13] but have never been thoroughly studied.…”

Section: Introductionmentioning

confidence: 99%

DRAM Characterization under Relaxed Refresh Period Considering System Level Effects within a Commodity Server

Mukhanov

Tovletoglou

Nikolopoulos

et al. 2018

2018 IEEE 24th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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The Dynamic Random Access Memory Challenge in Embedded Computing Systems

Jung

Weis

Wehn

2020

A Journey of Embedded and Cyber-Physical Systems

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Dynamic random access memories (DRAMs) are key components in all computing systems that require large working memory. Due to the strong increase in data volume in many embedded applications, such as machine learning, image processing, autonomous systems, etc., DRAMs largely impact the overall system performance and power consumption. In many of these applications, the overall system performance is often limited by the memory bandwidth or latency and not by the computation itself. Due to the dynamic storage scheme of DRAMs and shrinking technology nodes, reliability is also a major concern in current and future DRAMs. Therefore, new challenges arise, which we will discuss in this chapter. The most important metrics, which are typically considered for DRAM subsystems (especially in the high-performance computing (HPC) domain), are bandwidth, latency, and capacity. However, in the context of embedded systems it requires to consider further metrics, such as power, temperature, reliability, safety, and security. In the following we will highlight these challenges and refer to some of our recent contributions, which tackle these challenges.

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A Platform to Analyze DDR3 DRAM’s Power and Retention Time

Cited by 30 publications

References 11 publications

Workload-Aware DRAM Error Prediction using Machine Learning

Workload-Aware DRAM Error Prediction using Machine Learning

DRAM Characterization under Relaxed Refresh Period Considering System Level Effects within a Commodity Server

The Dynamic Random Access Memory Challenge in Embedded Computing Systems

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