A PLL configuration for reducing both incoming and inherent jitters

Abstract

In order to reduce jitters, both incoming and inherent, this article proposes a novel configuration. Feed-forward compensator improves jitter filtration, free from constraints on loop gain for reducing inherent jitters. Its effectiveness is verified on a prototype implemented on an FPGA, and experiments as a multiply-by-50 synthesizer result in 30-times reduction of inherent jitters and in halving of incoming jitters.