A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI

Yamamoto, Y.; Shirahama, M.; Kawasaki, Toshiaki; Nishihara, R.; Sumi, Shin'ichi; Agata, Y.; Kikukawa, H.; Yamauchi, Hiroyuki

doi:10.1093/ietele/e90-c.5.1129

Cited by 5 publications

(3 citation statements)

References 5 publications

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“…Similarly, Type II and III cells utilizing n-type gate tunneling device are expected to have a faster ejection speed due to the higher number of conduction band electrons compared with Types I and IV. In fact, the faster electron ejection speed of the Type II cell compared with Type I was previously theoretically predicted by other groups [6]. Similarly, the higher electron ejection current of an n+ poly FG compared with a p+ poly FG was reported in [7], which agrees with our measurement results in Fig.…”

Section: B Program and Erase Speed Of Single-poly Eflash Cellssupporting

confidence: 93%

“…For example, in [5], NCAP was used in the coupling (M 1 ) and tunneling (M 2 ) devices while pMOS was used in the read device (M 3 ). In another design [6], pMOS, NCAP, and nMOS were used in the coupling (M 1 ), erase (M 2 ), and program/read (M 3 ) devices, respectively, for the higher coupling ratios during program and erase operations. A workfunction engineered n+ poly pMOS was used as the tunneling device (M 2 ) in [7] for higher electron ejection efficiency and better reliability.…”

Section: Introductionmentioning

confidence: 99%

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A Comparative Study of Single-Poly Embedded Flash Memory Disturbance, Program/Erase Speed, Endurance, and Retention Characteristic

Song

Kim

2014

IEEE Trans. Electron Devices

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Single-poly embedded flash (eFlash) memory is a unique category of embedded nonvolatile memory (eNVM) that can be built in a generic logic technology. Several single-poly eFlash cells have been proposed for cost-effective moderate density eNVM applications. However, the optimal cell configuration of single-poly eFlash is still under debate. In this paper, we compared various single-poly eFlash memory structures in terms of disturbance, program/erase speed, endurance, and retention characteristic based on simulated and experimental data from two eFlash test chips fabricated in a generic 65-nm logic process using standard 2.5 V I/O transistors with 5-nm tunnel oxide. We conclude that a 5T eFlash cell structure combining a pMOS coupling device, an NCAP tunneling device, and an nMOS read/program device with two additional pass transistors to support self-boosting is the most attractive option for logic-compatible eNVMs.Index Terms-Embedded flash (eFlash) memory, embedded nonvolatile memory (eNVM), single-poly eFlash.

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Section: B Program and Erase Speed Of Single-poly Eflash Cellssupporting

confidence: 93%

Section: Introductionmentioning

confidence: 99%

A Comparative Study of Single-Poly Embedded Flash Memory Disturbance, Program/Erase Speed, Endurance, and Retention Characteristic

Song

Kim

2014

IEEE Trans. Electron Devices

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“…Non-volatile memories widely used for touch-screen controllers are OTP (One-time programmable) memories, EEPROMs and flash memories [1] [2]. Although OTP memories have been used widely and recently, MTP (Multitime programmable) memories are more suitable for multiple programming.…”

Section: Introductionmentioning

confidence: 99%

Design of a 256-KBit EEPROM IP for touch-screen controllers

Cho

Kim

Jang

et al. 2010

International Conference on Communications and Electronics 2010

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We propose a compact design having low-power and high-speed EEPROM for touch-screen controller ICs. To optimize a small-area EEPROM design, a SSTC (side-wall selective transistor) cell is proposed which involves repeated high-voltage switching circuits inside the EEPROM core circuit. A digital data-bus sensing amplifier circuit is proposed as a low-power technology. For high speed, the distributed data-bus scheme is applied, and the driving voltage for both the EEPROM cell and the high-voltage switching circuits uses VDDP (=3.3V) which is higher than the logic voltage, VDD (=1.8V), using a dual power supply. 256-KBit EEPROM IP is designed using MagnaChip's 0.18μm EEPROM process. The layout size of the designed 256-KBit EEPROM IP is 1765.05μm × 691.71μm.

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Program/erase speed, endurance, retention, and disturbance characteristics of single-poly embedded flash cells

Song

Kim

2013

2013 IEEE International Reliability Physics Symposium (IRPS)

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A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI

Cited by 5 publications

References 5 publications

A Comparative Study of Single-Poly Embedded Flash Memory Disturbance, Program/Erase Speed, Endurance, and Retention Characteristic

A Comparative Study of Single-Poly Embedded Flash Memory Disturbance, Program/Erase Speed, Endurance, and Retention Characteristic

Design of a 256-KBit EEPROM IP for touch-screen controllers

Program/erase speed, endurance, retention, and disturbance characteristics of single-poly embedded flash cells

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