A Polynomial-Time Algorithm for Memory Space Reduction

Song, Yonghong; Wang, Cheng; Li, Zhiyuan

doi:10.1007/s10766-004-1459-8

Cited by 3 publications

(1 citation statement)

References 17 publications

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“…Song et al [2004] proposed an aggressive array contraction and studied its impact on memory system performance. Song et al [2005] used an integer programming for modeling the problem of combining loop shifting, loop fusion, and array contraction. Lefebvre et al [1988] and Quillere and Rajopadhye [2000] proposed a memory reduction based on a multiprojection.…”

Section: Related Workmentioning

confidence: 99%

MPSoC memory optimization using program transformation

Bouchebaba

Girodias

Nicolescu

et al. 2007

ACM Trans. Des. Autom. Electron. Syst.

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Multiprocessor system-on-a-chip (MPSoC) architectures have received a lot of attention in the past years, but few advances in compilation techniques target these architectures. This is particularly true for the exploitation of data locality. Most of the compilation techniques for parallel architectures discussed in the literature are based on a single loop nest. This article presents new techniques that consist in applying loop fusion and tiling to several loop nests and to parallelize the resulting code across different processors. These two techniques reduce the number of memory accesses. However, they increase dependencies and thereby reduce the exploitable parallelism in the code. This article tries to address this contradiction. To optimize the memory space used by temporary arrays, smaller buffers are used as a replacement. Different strategies are studied to optimize the processing time spent accessing these buffers. The experiments show that these techniques yield a significant reduction in the number of data cache misses (30%) and in processing time (50%).

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Section: Related Workmentioning

confidence: 99%

MPSoC memory optimization using program transformation

Bouchebaba

Girodias

Nicolescu

et al. 2007

ACM Trans. Des. Autom. Electron. Syst.

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Optimizing inter-nest data locality in imperfect stencils based on loop blocking

2018

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Two-level tiling for MPSoC architecture

Bouchebaba

Bensoudane

Lavigueur

et al. 2007

2007 IEEE International Conf. On Application-Specific Systems, Architectures and Processors (ASAP)

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exploit the MPSoC architecture. The multimedia Multiprocessor systems-on-a-chip (MPSoCs architectures) applications often use temporary arrays to store have received a lot of attention in the past years, but few intermediate computations, to optimize the memory advances in compilation techniques target these space used by these temporary arrays, buffers and architectures. This is particularly true for the exploitation of registers are used as a replacement. several level of memory hierarchy. Usually tiling is applied to one loop nest; in this paper we apply simultaneously loop fusion with two-level tiling to several loop nests in the 2. Related work context of a MPSoC architecture. The two level-tiling allows The IMEC group [2] pioneered the work on program the simultaneous optimization of caches and registers. To transformations to reduce the energy consumption in optimize the memory space used by temporary arrays, data dominated embedded applications. Loop buffers and registers are used as a replacement. The transformation techniques, like loop fusion and tiling, experiments show that these techniques yield a significant are studied in several works [3] [8] [9]. The first work reduction in the number of data cache misses and in on tiling is given by Irigoin [5], who studied a processing time.sufficient condition to apply tiling to a single loop nest.

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A Polynomial-Time Algorithm for Memory Space Reduction

Cited by 3 publications

References 17 publications

MPSoC memory optimization using program transformation

MPSoC memory optimization using program transformation

Optimizing inter-nest data locality in imperfect stencils based on loop blocking

Two-level tiling for MPSoC architecture

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