A polynomial time triple patterning algorithm for cell based row-structure layout

Abstract

As minimum feature size keeps shrinking, and the next generation lithography (e.g, EUV) further delays, double patterning lithography (DPL) has been widely recognized as a feasible lithography solution in 20nm technology node. However, as technology continues to scale to 14/10nm, DPL begins to show its limitations and usually generates too many undesirable stitches. Triple patterning lithography (TPL) is a natural extension of DPL to conquer the difficulties and achieve a stitch-free layout decomposition. In this paper, we study the standard cell based row-structure layout decomposition problem in TPL. Although the general TPL layout decomposition problem is NP-hard, in this paper we will show that for standard cell based TPL layout decomposition problem, it is polynomial time solvable. We propose a polynomial time algorithm to solve the problem optimally and our approach has the capability to find all stitch-free decompositions. Color balancing is also considered to ensure a balanced triple patterning decomposition. To speed up the algorithm, we further propose a hierarchical algorithm for standard cell based layout, which can reduce the run time by 34.5% on average without sacrificing the optimality. We also extend our algorithm to allow stitches for complex circuit designs, and our algorithm guarantees to find optimal solutions with minimum number of stitches.

Toward Unidirectional Routing Closure in Advanced Technology Nodes

“…In general, there exist two types of MPL, Litho-Etch-Litho-Etch (LELE) type and self-aligned type. LELE-type of MPL allows stitch insertions and two-dimensional patterns [27], [59], [70], [71], [77], but coloring and overlay compensation schemes become extremely complicated for triple patterning lithography and beyond [12], [15], [30], [38], [60], [73], [76], [81]. Self-aligned type of MPL can minimize electrical variations from overlay and line-edge-roughness but introduces complex coloring and line-end constraints [40], [42], [56].…”

Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography

“…Triple patterning lithography (TPL) is one of the most promising techniques in the 14 nm logic node and beyond. In order to realize a target pattern, various types of techniques including design for manufacturability, such as LELE type double patterning lithograph [1][2][3][4][5][6][7], LELELE type TPL [8][9][10][11][12][13][14][15][16][17][18], LELECUT type TPL [19], and side wall process [20], are used in addition to a basic litho-etch process with optimized mask. These techniques are summarized in [21,22].…”

“…LELELE type TPL technology [8][9][10][11][12][13][14][15][16][17][18] in which litho-etch process is repeated three times is often discussed in literature. However, it suffers from native conflict and overlay problems.…”

Constrained pattern assignment for standard cell based triple patterning lithography

“…Plenty of research efforts have been devoted to TPL [4], [11], [18], [19], [22] [3], [13], [15]- [17]. Bei Yu et al showed that the general TPL decomposition problem is NP-hard, and further proposed an ILP based algorithm to compute legal TPL solutions [22].…”

“…Experimental results verify that the problem can be solved very efficiently with the proposed algorithm. Superior locally balanced decompositions are achieved compared with the previous approach in [19].…”