A portable redundancy algorithm for capacitive/resistive SAR A/D converters

Zamprogno, Marco; Minuti, Alberto; Girardi, Francesca; Devecchi, Daniele; Nicollini, G.

doi:10.1109/icecs.2013.6815374

Cited by 1 publication

(1 citation statement)

References 9 publications

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“…Switching schemes such as correlated reverse switching [31] can reduce the maximum σINL,best-fit and σDNL by a factor of √2 or more. Furthermore, non-binary techniques can be combined with DAC calibration to achieve superior static linearity performance when a generalized non-binary algorithm is used [45][46][47][48][49]. In general, the number of CDAC switches increases with the resolution of the CDAC and the number of reference voltages implemented.…”

Section: Dac Switching Techniquesmentioning

confidence: 99%

Low-power high-performance SAR ADC with redundancy and digital error-correction

Sharma¹

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The demands for data converters have soared in the last decade with the boom in consumer electronics, smart devices, autonomous vehicles, and automotive segments. The current trend among Nyquist-rate data converters, for example successive approximation register (SAR) analog-to-digital converters (ADC), tends towards high speeds and medium-to-high resolution. Applications such as vehicleto-everything (V2X) communication, wireless internet of things, test systems, etc., benefit from high-speed and high resolution ADCs. An in-depth analysis of data converter trends, and current state-of-the-art SAR ADCs are discussed. The topics discussed include data converters using binary and non-binary redundancy techniques, digital error correction schemes, DAC switching schemes, and associated hardware overheads. This thesis focuses on six important contributions to high speed and medium resolution SAR ADC research. The first one is the introduction of binary-scaled redundancy embedded in the conventional capacitive DAC (CDAC), and the second is optimizing the use of redundancy by introducing a new CDAC switching scheme. The third contribution introduces a simple "bit overlap and add" digital error correction-technique for a 10-bit SAR ADC. Multiple erroneous decisions can be corrected over nine conversion cycles, independent of where the erroneous conversion cycle occurred. The implementation of the technique requires no additional conversion cycles to obtain a 10-bit resolution. Fourth, this thesis introduces a new area-efficient switching scheme for a multi-bit per cycle SAR ADC. The proposed constant common-mode fractional reference voltage (CCM

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Section: Dac Switching Techniquesmentioning

confidence: 99%

Low-power high-performance SAR ADC with redundancy and digital error-correction

Sharma¹

View full text Add to dashboard Cite

show abstract

A portable redundancy algorithm for capacitive/resistive SAR A/D converters

Cited by 1 publication

References 9 publications

Low-power high-performance SAR ADC with redundancy and digital error-correction

Low-power high-performance SAR ADC with redundancy and digital error-correction

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