A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug

Cao, Yuting; Zheng, Hao; Palombo, Hernan; Ray, Sandip; Yang, Jian

doi:10.1109/iccd.2017.35

Cited by 7 publications

(2 citation statements)

References 12 publications

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“…A flow is a collection of messages as nodes and edges as their causal relation expressed as a directed graph. Several previous works [22] have formalized the message flow mining problem in the literature.…”

Section: Message Flows Causality Graph Language Modelsmentioning

confidence: 99%

Mining SoC Message Flows with Attention Model

Ahmed¹,

Bardia²,

Zheng³

2022

Preprint

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High-quality system-level message flow specifications are necessary for comprehensive validation of system-on-chip (SoC) designs. However, manual development and maintenance of such specifications are a daunting task. We propose a disruptive method that utilizes deep sequence modeling with the attention mechanism to infer accurate flow specifications from SoC communication traces. The proposed method can overcome the inherent complexity of SoC traces induced by the concurrent executions of SoC designs that existing mining tools often find extremely challenging. We conduct experiments on five highly concurrent traces and find that proposed approach outperforms several existing state-of-the-art trace mining tools.

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Section: Message Flows Causality Graph Language Modelsmentioning

confidence: 99%

Mining SoC Message Flows with Attention Model

Ahmed¹,

Bardia²,

Zheng³

2022

Preprint

Self Cite

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“…Many existing post-silicon debug technique can benefit from PRoN and its improved functionally relevant signals. These include trace analysis-based SoC protocol debug [14], [38], post-silicon validation and trace signal selection via bitflip detection [34], [35], post-silicon bug localization, and validation for processors [24], [28], [29], [36].…”

Section: Related Workmentioning

confidence: 99%

Emphasizing Functional Relevance Over State Restoration in Post-Silicon Signal Tracing

Pal

Vasudevan

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The state restoration ratio (SRR) has been a de facto standard for evaluating the quality of signals selected for postsilicon tracing and debug. In this paper, we establish that SRR is intrinsically unsuitable as a metric for evaluating trace signal quality, as it captures neither the higher-level functionality of the design nor the constraints and requirements on trace signals. We present an algorithm, based on PageRank [PageRank on Netlist (PRoN)], for post-silicon trace signal selection. PageRank is not designed to maximize SRR and is applied to the circuit netlist. We demonstrate that optimizing for SRR typically generates signals that are functionally irrelevant to the design and unusable for debug, for a comprehensive set of SRR-based techniques. We assess the scalability of different signal selection algorithms by applying them to an industrial scale OpenSPARC T2 design. Our results show that our PRoN algorithm consistently outperformed other techniques with respect to scalability and functional relevance of signals selected. It also has higher restorability than the other algorithms, despite not being optimized for that metric.

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