A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs

Chickermane, V.; Gallagher, Patrick; Sage, Jeremy; Yuan, Peng; Chakravadhanula, Krishna

doi:10.1109/test.2008.4700572

Cited by 16 publications

(11 citation statements)

References 11 publications

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“…In order to reduce the functional power consumption, various low power management techniques have to be implemented during design phase [1][2][3][4][5]:…”

Section: Open Accessmentioning

confidence: 99%

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Low Power Testing—What Can Commercial Design-for-Test Tools Provide?

Lin

2011

JLPEA

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“…In order to reduce the functional power consumption, various low power management techniques have to be implemented during design phase [1][2][3][4][5]:…”

Section: Open Accessmentioning

confidence: 99%

“…To improve the testability for the power management circuitry, DFT structure, such as the Power Test Access Mechanism (PTAM) [2], can be inserted in the design by using the DFT insertion tool. During test, this structure generates signals that override the control signals from the functional power controller.…”

Section: Testing Of Power Management Circuitrymentioning

confidence: 99%

Low Power Testing—What Can Commercial Design-for-Test Tools Provide?

Lin

2011

JLPEA

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“…Previous researches on low power had established various approaches such as clock gating [13], buffer insertion and sizing [14], multi-voltage designs [15]. Among these approaches, clock gating used widely in high performance VLSI designs has been implanted to FPGA clock network.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of clock network for nanometer FPGA

Lai

2015

IEICE Electron. Express

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This paper is committed to design and implement FPGA clock network with overall considerations of speed and power in circuit design perspective. Mixed structure MUX, programmable delay adjustment unit and power-down bit strategies are presented to optimize its latency, skew and power. This clock network is implemented with 65 nm process and applied to own-designed FPGA. Test results indicate 21.7% reduction in latency and 54.5% reduction in skew, compared to counterpart FPGA device, while maintaining lower power consumption.

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“…Sometimes, based on the application need, separate voltage domains are deployed for processor domains. The physical design and design validation complexity increases significantly when powerdomain or voltage domains are deployed in multicore designs [2].…”

Section: Introductionmentioning

confidence: 99%

State Retention Validation of C66X DSP Core

Venkatasubramanian

Olorode

Arun

2013

2013 14th International Workshop on Microprocessor Test and Verification

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Low power design has become an important design requirement in any deep-submicron CMOS design development. State retention using retention flip flops is one of the low power techniques that offer the ability to save and restore the state of the design during a period of inactivity (IDLE or STANDBY mode). Since processor cores typically have a well-defined period of operation and inactivity, the state retention scheme is well suited for processor designs. This paper provides an overview of the various state retention implementation choices for processor cores and explains the state retention validation methodology for the different implementations. The state retention and validation methodology deployed for the TI C66x Core is explained in detail.

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A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs

Cited by 16 publications

References 11 publications

Low Power Testing—What Can Commercial Design-for-Test Tools Provide?

Low Power Testing—What Can Commercial Design-for-Test Tools Provide?

Design and implementation of clock network for nanometer FPGA

State Retention Validation of C66X DSP Core

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