A power-efficient 14.8-GHz CMOS programmable frequency divider with quadrature outputs in 40-nm CMOS process

Huang, Sen; Diao, Shengxi; Lin, Fujiang

doi:10.1007/s10470-017-1037-9

Analog Integr Circ Sig Process

2017

DOI: 10.1007/s10470-017-1037-9

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A power-efficient 14.8-GHz CMOS programmable frequency divider with quadrature outputs in 40-nm CMOS process

Sen Huang

Shengxi Diao

Fujiang Lin

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A power-efficient 14.8-GHz CMOS programmable frequency divider with quadrature outputs in 40-nm CMOS process

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References 29 publications

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