A Power-Efficient Linearized Open-Loop OTA Utilizing Reconfigurable Tail-Resistor Pair

Chen, Xi; Wang, Keping; Liao, Hong Shu; Ma, Shiyue; Ma, Kaixue

doi:10.1109/tcsii.2023.3260925

Cited by 2 publications

(2 citation statements)

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“…In single‐slope ADCs, open‐loop amplifiers are commonly used as comparators because of the simple structure and low‐power consumption requirements of a typical column‐parallel circuit structure. Despite not having a negative‐feedback path for a precise amplification, an open‐loop amplifier can provide fast speed and high gain while offering low‐power consumption [15, 16].…”

Section: Single‐slope Adc Structurementioning

confidence: 99%

“…In single-slope ADCs, open-loop amplifiers are commonly used as comparators because of the simple structure and low-power consumption requirements of a typical column-parallel circuit structure. Despite not having a negative-feedback path for a precise amplification, an openloop amplifier can provide fast speed and high gain while offering lowpower consumption [15,16]. The proposed comparator comprises a two-stage operational amplifier (OPAMP) for performing the comparison operation and amplification that provides signal gain to the output signal.…”

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confidence: 99%

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A 10‐bit 13.3 µW single‐slope analog‐to‐digital converter with auto‐zero power‐down technique

Lee,

Kim,

Jun

2024

Electronics Letters

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This letter presents a low‐power single‐slope analog‐to‐digital converter (ADC) for column‐parallel architectures. A simple and effective design technique is proposed to solve the input‐dependent power consumption problem of the conventional single‐slope ADCs. A decision‐feedback loop is implemented in the second stage of the comparator. Based on the negative‐feedback path, which is activated after the signal decision of the comparator, the input‐dependent dynamic current path in the amplifier is disabled. Furthermore, an additional low‐power design technique is proposed to save the power consumption of the ADC by optimizing the offset cancelling auto‐zero period. With the combination of the proposed techniques, the power consumption of the single‐slope ADC can be effectively saved while suppressing the dynamic current.

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Section: Single‐slope Adc Structurementioning

confidence: 99%

mentioning

confidence: 99%