A power-efficient network on-chip topology

Camacho, Jesús; Flich, José; Duato, J.; Eberle, Hans; Olesinski, W.

doi:10.1145/1930037.1930044

Cited by 8 publications

(6 citation statements)

References 12 publications

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“…The area is improved by reducing the number of cells as well as to replace by a cell that can perform multiple functions. The time taken by the data to travel from one point to the other is known as latency . It depends on the actual distance the data requires to travel through the networks and cord to reach its destination.…”

Section: Resultsmentioning

confidence: 99%

“…In some introduced approaches, the distance between the network architectures is reduced in the architecture to increase the efficiency of the network. In order to lessen the distance between the nodes within a network, Camacho et al introduced diagonal channels to enhance the performance of the network. Therefore, the architecture requires a router to increase the ports in all directions, which, in turn, increases the cost of the system.…”

Section: Relevant Researchesmentioning

confidence: 99%

“…The time taken by the data to travel from one point to the other is known as latency. 7 It depends on the actual distance the data requires to travel through the networks and cord to reach its destination. The comparison of the area and latency of the existing and the proposed ScMesh topology of 180 nm and 45 nm are given in Table 1.…”

Section: Asic Synthesismentioning

confidence: 99%

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An area‐efficient low‐power SCM topology for high performance network‐on Chip (NoC) architecture using an optimized routing design

Poovendran¹,

Sumathi²

2018

Concurrency and Computation

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Summary The incorporation of network‐on‐Chip with communication delivers a strengthening solution to the rising complexity and problems in system‐on‐chip. Here, mesh topology is shortly connected, utilizing the symmetric properties of the network, and is introduced. In addition, 4x4‐Router Architecture–Carry Select Adder (4x4‐RA‐CSLA) method is proposed to improve the function of the Router Architecture (RA) in the network. These features make the system achieve efficient architecture in terms of lower area and power for the interconnection of network scenarios. This new architecture is debugged using ModelSim with Verilog code. The experimental result shows improvement in area and power.

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Section: Resultsmentioning

confidence: 99%

Section: Relevant Researchesmentioning

confidence: 99%

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An area‐efficient low‐power SCM topology for high performance network‐on Chip (NoC) architecture using an optimized routing design

Poovendran¹,

Sumathi²

2018

Concurrency and Computation

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“…Já em [Camacho et al 2011], foi proposta uma NoC denominada NR-Mesh. O princípio dessa NoC, baseada em uma topologia Mesh,é o uso de roteadores diferentes do que o núcleo está conectado para enviar e receber mensagens pela rede.…”

Section: Trabalhos Relacionadosunclassified

Avaliação de Topologias de Redes-em-Chip usando Simulação de Sistemas Completos e Aplicações Paralelas

Carmo¹,

Souza²,

Freitas³

2016

Anais Do XVII Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2016)

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A abordagem de Redes-em-Chip é uma alternativa na busca por poder de processamento. Ao invés de usar sistemas de interconexão tradicionais, essa estratégia utiliza roteadores para permitir a comunicação entre os núcleos de um processador many-core. Porém, o desempenho do processador pode ﬁcar comprometido caso o projeto de interconexão não esteja bem planejado. A degradação da largura de banda e a presença de desbalanceamento de cargas entre os componentes do processador podem reduzir o desempenho destas arquiteturas. Este trabalho tem como objetivo mostrar como o desempenho do processador pode ser afetado pela topologia da rede-em-chip e o projeto para interconectar as memórias. Os resultados mostraram que as arquiteturas organizadas em cluster apresentaram desempenho melhor em relação as outras arquiteturas.

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“…In addition, it doesn't ensure routing flexibility due to the limitation of resources. A number of studies have attempted to address this shortcoming by adding application-specific links between distant nodes in the mesh [12], by leaving out intermediate nodes for express channels to reduce hop counts [13], by changing the network diameter in topologies related to the mesh, by adding 2D digraph families to increase network performance [14], or by inserting additional links into the mesh topology [15].…”

Section: Research Motivationsmentioning

confidence: 99%

An Extended Diagonal Mesh Topology for Network-on-Chip Architectures

Furhad

Kim

2015

IJMUE

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This paper proposes an extended diagonal mesh (XDMesh) topology for network-onchip (NoC) architectures to reduce latency and energy consumption for fast and lowpower communication among remote nodes by including diagonal links in the network. In addition, we compare the performance of the proposed XDMesh with conventional stateof-the art topologies, including mesh, extended-butterfly fat tree (EFTI), and diametrical mesh, in terms of throughput, latency, energy consumption, and area overhead. Experimental results indicate that XDMesh outperforms the conventional topologies in terms of throughput and latency by varying the number of virtual channels and injection rate. Moreover, XDMesh achieves 46.28%, 35.29% and 19.37% lower energy consumption than EFTI, mesh, and diametrical mesh topologies, respectively, and 9.29%, 31.28%, and 15.23% lower silicon area, respectively. 198Copyright ⓒ 2015 SERSC throughput, high bandwidth, reusability, and lower power consumption for communication can be achieved with NoC-based architectures [6].A number of topologies have been proposed in previous studies of NoCs, primarily derived from traditional data communication network topologies. Some examples of NoC topologies include mesh [7], extended-butterfly fat tree (EFTI) [8], and diametrical mesh (DiaMesh) [9]. Among these, the mesh topology is preferred by NoC designers due to its modularity and scalability. Since the two-dimensional mesh perfectly matches the 2D silicon surface, it is currently the most popular topology used for NoCs in tile-based architectures. Moreover, a 2D mesh topology can be partitioned into smaller meshes, which is a desirable feature for many parallel applications [10]. However, the conventional mesh topology of NoC architecture increases the number of hops when distant nodes communicate with each other, thereby increasing the system size. It requires higher energy consumption, and longer clock cycles to accomplish the communication.To solve this problem inherent in the mesh topology, we propose an extended diagonal mesh (XDMesh) topology that considers the location of nodes situated in remote regions by including diagonal links among these remote regions, which reduces the hop count, latency, energy consumption, and area cost.The rest of this paper is organized as follows. Section 2 discusses related studies of NoC. Section 3 describes the proposed XDMesh topology and its routing algorithm. Section 4 presents the experimental results and analysis. Finally, Section 5 provides conclusions for the paper.

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A power-efficient network on-chip topology

Cited by 8 publications

References 12 publications

An area‐efficient low‐power SCM topology for high performance network‐on Chip (NoC) architecture using an optimized routing design

An area‐efficient low‐power SCM topology for high performance network‐on Chip (NoC) architecture using an optimized routing design

Avaliação de Topologias de Redes-em-Chip usando Simulação de Sistemas Completos e Aplicações Paralelas

An Extended Diagonal Mesh Topology for Network-on-Chip Architectures

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