A power-efficient scan tree design by exploring the Q'-D connection

Chen, Linfeng; Cui, Aijiao

doi:10.1109/iscas.2013.6572022

Cited by 3 publications

(1 citation statement)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Amit Mishra [9] proposed a modified scan flip-flop for low power testing in which the flip-flop disables the slave latch during scan and uses an alternate low cost dynamic latch. There are different latches and flipflops with many different techniques are proposed in [14][15][16] to reduce power and delay during testing. This paper presents the consolidated research work for power optimized testing of VLSI chips.…”

Section: Fig 1: Block Diagram Of Scan Flopmentioning

confidence: 99%

Techniques for Low Power and Area Optimized VLSI Testing using Novel Scan Flip-Flop

Jayagowri¹

2015

IJCA

View full text Add to dashboard Cite

Power consumption of any circuit is high during test mode than its normal mode of functioning. Different techniques are proposed to reduce the test power. This paper presents the consolidated research work carried to reduce the test power. Usually the power dissipation is due to the sequential and combinational elements presents in the circuit. In this paper we proposed different methodologies and they are at cell level optimization to reduce test power. The structure of the scan flip-flop is modified to reduce the power due to sequential elements and gating techniques are proposed to reduce power duo to combinational elements. The proposed methodologies are implemented on the different ISCAS benchmark circuit and the experimental results were observed. These experimental results showed that our proposed methods reduced the switching power by 44.58-61.97%including the proposed gating technique, area by 30-45% and the test time by 50%.

show abstract