A Power-Efficient Tunable Narrow-Band Digital Front End for Bandpass Sigma–Delta ADCs in Digital FM Receivers

Abstract

A power-efficient narrow-band tunable digital front end (DFE) for bandpass sigma-delta (ΣΔ) analog-to-digital converters is presented. The proposed architecture introduces a new system topology, splitting the down converter into two mixers and placing a cascaded integrator-comb decimation stage between the two mixers. The first mixer is a quadrature mixer that works at a quarter of the sampling frequency. It is followed by a complex mixer with a tunable frequency. The ΣΔ modulator and the DFE are digitally controlled. The proposed architecture is first analyzed on the system level and then synthesized in a 130-nm CMOS technology. A reduction in the power consumption of about 50% has been achieved by the proposed architecture when compared with the conventional approach.Index Terms-Cascaded integrator comb (CIC), digital front end (DFE), frequency modulation (FM), low power, polyphase decimator, tunable.

Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

“…Similar to the aforementioned example design options 1, 2, and 3, various candidates in the architecture design space were evaluated before the final DFE architecture was proposed. A multitude of literatures deal with the DFE, including [2][3][4][5][6][7][8][9][11][12][13]17,[27][28][29][30], and many of them are based on the CIC filter, Farrow interpolator, and the FIR filter. However, most of them address only the simulated results and few of them explain the ASIC or FPGA implementation in detail.…”

“…The filter bank is in turn based on decimation and interpolation. A tunable narrow-band digital front-end for delta-sigma ADCs is simulated in [11], which starts with a quadrature mixer followed by a complex mixer (with a tunable frequency) and a cascaded integrator comb decimator in between. A look-up table based numerically controlled oscillator is coupled with the mixers.…”

Low power area optimized novel architecture for Software Defined Radio in FPGA

“…Ed(n) = Km * [sin(wn + e) cos(wn + <p)] Ed(n) = .5 * Km * sin(2wn + e + <p) * sinCe -<p) (4) Km is the gain of the phase detector. The first term and second tenn in (3) represents high frequency components and phase differences respectively.…”

“…In order to maximize the data rate, the digital bandwidth is increased which is subjected to a maximum allowed distortion of the demodulated analog FM signal. An efficient narrow-band Digital Front End (DFE) for band pass sigma-delta (LL1) analog-to-digital converters is suggested in [4]. The proposed architecture introduces a new system topology, which splits the down converter into two mixers and places cascaded integrator-comb decimation between the two mixers.…”