A Power, Performance Scalable Eight-Cores Media Processor for Mobile Multimedia Applications

Mori, Tatsuya; Ueda, Yasuyuki; Nonogaki, Nobuhiro; Terazawa, T.; Sroka, Milosz; Fujita, Takeshi; Kodaka, Takeshi; Morita, K.; Arakida, Hideho; Miura, Tadao; Okuda, Yukihiko; Kizu, Toshiki; Tsuboi, Y.

doi:10.1109/jssc.2009.2028936

Cited by 20 publications

(7 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In Table X, we compare the decoding performance data of the REMUS_LPP processor with the ADRES reconfigurable processor [8], a DSP based video decoder chip [36] developed for multi-format set-top box and another video codec chip [37]. From the normalized performance data, one can see that the REMUS_LPP processor achieves a 16% faster decoding speed than both the ADRES reconfigurable processor and the DSP chip.…”

Section: B Evaluation and Comparison 1) Performancementioning

confidence: 99%

“…From the normalized performance data, one can see that the REMUS_LPP processor achieves a 16% faster decoding speed than both the ADRES reconfigurable processor and the DSP chip. When compared with the video codec chip presented in [37], the performance of the REMUS_LPP processor is 1.28× lower. The very high decoding speed achieved by [37] benefits from the 3.44 times higher working frequency adopted.…”

Section: B Evaluation and Comparison 1) Performancementioning

confidence: 99%

See 1 more Smart Citation

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

Liu

Wang

Zhu

et al. 2015

IEEE Trans. Multimedia

View full text Add to dashboard Cite

A coarse-grained Reconfigurable Processing Unit (RPU) consisting of 16×16 multi-functional Processing Elements (PEs) interconnected by an area-efficient Line-Switched Mesh Connect (LSMC) routing is implemented on a 5.4mm×3.1mm die in TSMC 65 nm LP1P8M CMOS technology. A Hierarchical Configuration Context (HCC) organization scheme is proposed to reduce the implementation overhead and the energy dissipation spent on fast reconfiguration. The proposed RPU is integrated into two System-on-a-Chips (SoCs), targeting multiple-standard video decoding. The high-performance chip, comprising two RPU processors (named REMUS_HPP), can decode 1920×1080 H.264 video streams at 30 frames per second (fps) under 200 MHz. REMUS_HPP achieves a 25% performance gain over the XPP-III reconfigurable processor with only 280 mW power consumption, resulting in a 14.3× improvement on energy efficiency. The other chip (named REMUS_LPP), targeting low power applications, integrates only one RPU processor. REMUS_LPP can decode 720×480 H.264 video streams at 35fps with 24.5 mW under 75 MHz, achieving a 76% reduction in power dissipation and a 3.96× improvement on energy efficiency compared with the ADRES reconfigurable processor. IndexTerms-Coarse-grained reconfigurable array, reconfigurable computing, video decoding.

show abstract

Section: B Evaluation and Comparison 1) Performancementioning

confidence: 99%

Section: B Evaluation and Comparison 1) Performancementioning

confidence: 99%

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

Liu

Wang

Zhu

et al. 2015

IEEE Trans. Multimedia

View full text Add to dashboard Cite

show abstract

“…CELL includes data-parallel synergistic processing units, GPUs support many lightweight data-parallel threads, and the Strom-1 processor utilizes an optimized ALU and memory architecture for kernel and stream data processing with different ILP and DLP. In terms of its chip multiprocessor (CMP) or multi-core architecture, the proposed streaming architecture is more like Intel 80-Tile processor [12] and Toshiba's eight-core media processor [13] that process streams as threads in different cores. These multi-core processors exploit a packet-switched NoC and pipeline-based/thread-based parallel execution schemes for high computing power respectively.…”

Section: B Related Workmentioning

confidence: 99%

“…In comparison to those processors, while exploiting the high-performance technologies of the multi-core architectures, the proposed processor is much more power efficient due to its use of fixed-point ALUs instead of floating-point ALUs as well as its use of 2-D direct memory access (DMA)-integrated NoC interfaces instead of a cache-based memory system that requires a power-hungry hierarchical memory architecture. Therefore, the processor can achieves higher computing power with lower power consumption compared to the multi-core processors [12], [13] and, also, SIMD-based parallel machines such as IMAPCAR and Xetal-II [14].…”

Section: B Related Workmentioning

confidence: 99%

A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams

Kim

Park

et al. 2013

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

Abstract-A heterogeneous multi-core processor is proposed to achieve real-time dynamic object recognition on HD 720p video streams. The context-aware visual attention model is proposed to reduce the required computing power for HD object recognition based on enhanced attention accuracy. In order to realize real-time execution of the proposed algorithm, the processor adopts a 5-stage task-level pipeline that maximizes the utilization of its 31 heterogeneous cores, comprising four simultaneous multithreading feature extraction clusters, a cache-based feature matching processor and a machine learning engine. Dynamic resource management is applied to adaptively tune thread allocation and power management during execution based on the detected amount of tasks and hardware utilization to increase energy efficiency. As a result, the 32 mm chip, fabricated in 0.13 m CMOS technology, achieves 30 frame/sec with 342 8-bit GOPS peak performance and 320 mW average power dissipation, which are a 2.72 times performance improvement and 2.54 times per-pixel energy reduction compared to the previous state-of-the-art.Index Terms-Multi-core processor, object recognition, scale invariant feature transform, heterogeneous, low power processor, dynamic resource management, dynamic voltage and frequency scaling. GLOSSARY OF ABBREVIATIONS GOPS

show abstract

“…In the Full HD case, if the working frequency of the processor is 400 MHz, the allowable processing time for each pixel is 6.43 cycles (400 M/(1,920 × 1,080 × 30)). Uniprocessor architecture is not efficient in supporting such a high performance requirement; therefore, multiprocessor-based architectures are being adopted [3], [4], [5] to support high com- In designing a high performance multiprocessor architecture for the image processing engine, the capability of processing element and communication architecture which is used to connect the processing elements are essential issues. The common hardware types of processing element on the market can be classified into ASIC, reconfigurable ASIC, Application specific instructionset processor (ASIP), DSP and general purpose processor (GPP).…”

Section: Introductionmentioning

confidence: 99%

Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing

Liao

Asri

Isshiki

et al. 2013

Journal of Information Processing

View full text Add to dashboard Cite

An image processing engine is an important component in generating high quality images in video systems. Processing during capture and display are non-standard and vary from case by case, hence, the flexibility of image processing engines has turned out to be an important issue. The conventional hardware type of image processing engine such as an Application Specific Integrated Circuit (ASIC) is not applicable for this case. In order to increase design reusability and ease time-to-market pressures, Application Specific Instruction-set Processors (ASIP) which provide high flexibility and high computational efficiency have emerged as a promising solution. In this paper, we present two ASIPs. PXL ASIP, which has a reconfigurable multi bank memory module and an SIMD type computation pipeline, is designed for pixel level image processing, while 2D ASIP, which has slide register module and reconfigurable ALU modules, is designed for 2D image processing. PXL ASIP can perform 4 to 10 times faster compared to its base processor, and 2D ASIP can perform 5 to 43 times faster compared to its base processor.

show abstract

A Power, Performance Scalable Eight-Cores Media Processor for Mobile Multimedia Applications

Cited by 20 publications

References 11 publications

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams

Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing

Contact Info

Product

Resources

About