A Practical Encrypted Microprocessor

Breuer, Peter T.; Bowen, Jonathan P.; Palomar, Esther; Liu, Zhiming

doi:10.5220/0005955902390250

Cited by 11 publications

(7 citation statements)

References 13 publications

(13 reference statements)

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“…Cryptoleq also depends on heuristic code-based obfuscation. There is a Open RISC implementation based on idea of HEROIC [53], but this is suffered from too much memory consumption because of big tables. The authors estimated it to be between hundreds of gigabytes to terabytes.…”

Section: A1 Processor Over Hementioning

confidence: 99%

Virtual Secure Platform: A Five-Stage Pipeline Processor over TFHE

Matsuoka,

Banno,

Matsumoto

et al. 2020

Preprint

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We present Virtual Secure Platform (VSP), the first comprehensive platform that implements a multi-opcode generalpurpose sequential processor over Fully Homomorphic Encryption (FHE) for Secure Multi-Party Computation (SMPC). VSP protects both the data and functions on which the data are evaluated from the adversary in a secure computation offloading situation like cloud computing. We proposed a complete processor architecture with a five-stage pipeline, which improves the performance of the VSP by providing more parallelism in circuit evaluation. In addition, we also designed a custom Instruction Set Architecture (ISA) to reduce the gate count of our processor, along with an entire set of toolchains to ensure that arbitrary C programs can be compiled into our custom ISA. In order to speed up instruction evaluation over VSP, CMUX Memory based ROM and RAM constructions over FHE are also proposed. Our experiments show that both the pipelined architecture and the CMUX Memory technique are effective in improving the performance of the proposed processor. We provide an open-source implementation of VSP which achieves a per-instruction latency of less than 1 second. We demonstrate that compared to the best existing processor over FHE, our implementation runs nearly 1,600× faster.

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Section: A1 Processor Over Hementioning

confidence: 99%

Virtual Secure Platform: A Five-Stage Pipeline Processor over TFHE

Matsuoka,

Banno,

Matsumoto

et al. 2020

Preprint

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“…Hardware aliasing arises nowadays notably in the context of encrypted computing [7,8,9,10,11,12,13]. That emerging technology is based on a processor in which inputs, outputs, and all intermediate values exist only in encrypted form.…”

Section: Introductionmentioning

confidence: 99%

Safe Compilation for Hidden Deterministic Hardware Aliasing

Breuer¹,

Bowen

2019

2019 IEEE International Symposium on Software Reliability Engineering Workshops (ISSREW)

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Hardware aliasing occurs when the same logical address can access different physical memory locations. This is a problem for software on some embedded systems and more generally when hardware becomes faulty in irretrievable locations, such as on a Mars Lander. We show how to work around the hardware problem with software logic, compiling code so it works on any platform with hardware aliasing with hidden determinism. That is: (i) a copy of an address accesses the same location, and (ii) repeating an address calculation exactly will repeat the same access again. Stuck bits can mean that even adding zero to an address can make a difference in that environment so nothing but a systematic approach has a chance of working. The technique is extended to generate aliasing as well as compensate for it, in so-called chaotic compilation, and a sketch proof is included to show it may produce object code that is secure against discovery of the programmer's intention. A prototype compiler implementing the technology covers all of ANSI C except longjmp/setjmp.

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“…This article explains recent advances in understanding and practice in the emerging technology of encrypted computing [1][2][3][4][5][6], in particular 'chaotic compilation' for this context [7], which supports the security proofs and now has broken through to allow essentially all extant ANSI C [8] source codes to be compiled (the known lacks are longjmp/setjmp), nearly as they stand (strict typing is necessary), opening up the field. An unexpected byproduct is an argument that obfuscation safe against polynomial time attacks is produced by this kind of compilation, perhaps even in the absence of encryption.…”

Section: Introductionmentioning

confidence: 99%

Chaotic Compilation for Encrypted Computing: Obfuscation but Not in Name

Breuer¹

2019

Preprint

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An 'obfuscation' for encrypted computing is quantified exactly here, leading to an argument that security against polynomial-time attacks has been achieved for user data via the deliberately 'chaotic' compilation required for security properties in that environment. Encrypted computing is the emerging science and technology of processors that take encrypted inputs to encrypted outputs via encrypted intermediate values (at nearly conventional speeds). The aim is to make user data in generalpurpose computing secure against the operator and operating system as potential adversaries. A stumbling block has always been that memory addresses are data and good encryption means the encrypted value varies randomly, and that makes hitting any target in memory problematic without address decryption, yet decryption anywhere on the memory path would open up many easily exploitable vulnerabilities. This paper 'solves (chaotic) compilation' for processors without address decryption, covering all of ANSI C while satisfying the required security properties and opening up the field for the standard software tool-chain and infrastructure. That produces the argument referred to above, which may also hold without encryption.

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A Practical Encrypted Microprocessor

Cited by 11 publications

References 13 publications

Virtual Secure Platform: A Five-Stage Pipeline Processor over TFHE

Virtual Secure Platform: A Five-Stage Pipeline Processor over TFHE

Safe Compilation for Hidden Deterministic Hardware Aliasing

Chaotic Compilation for Encrypted Computing: Obfuscation but Not in Name

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