A practical evaluation of I/sub DDQ/ test strategies for deep submicron production test application. Experiences and targets from the field

Fudoli, A.; Ascagni, A.; Appello, D.; Manhaeve, H.

doi:10.1109/etw.2003.1231670

Cited by 6 publications

(1 citation statement)

References 12 publications

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“…Low-V T transistors used in high-performance logic are particularly prominent contributors to I back . This problem is addressed by design measures as well as by a number of advanced test methodologies like relative IDDQ, current ratios, current signatures, and Delta-IDDQ [2,3]. In this work we will consider Delta-IDDQ testing.…”

Section: Introductionmentioning

confidence: 99%

Delta-IDDQ Testing of Resistive Short Defects

Engelke¹,

Polian²,

Manhaeve³

et al. 2006

2006 15th Asian Test Symposium

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Section: Introductionmentioning

confidence: 99%

Delta-IDDQ Testing of Resistive Short Defects

Engelke¹,

Polian²,

Manhaeve³

et al. 2006

2006 15th Asian Test Symposium

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Current Testing for Nanotechnologies: A Demystifying Application Perspective.

Manhaeve¹

2005

14th Asian Test Symposium (ATS'05)

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The Advent of Nanotechnology imposes challenges on current based testing which existing ATE embedded solutions do not properly address. Luckily alternative solutions are available that not only overcome the challenges but meanwhile also help to improve screening efficiency, reduce test efforts, time and cost without compromising on test and product quality and even are offering ways to improve the latter. The contribution will consider this as well as the application requirements of such advanced add-on IDDQ measurement solutions and illustrates their application and achievable benefits on base of a number of real-life case studies. At the end conclusions will be drawn and guidelines for the future will be presented.Nanotechnologies impose challenges related to growing device complexity and higher integration densities. As a result, the total normal leakage is often one or more orders of magnitude higher than the defect current, rendering the Traditional IDDQ approach invalid. However advanced IDDQ screens supported by proper measurement solutions are paving the pathway to even a more advantageous use of current testing. In addition various solutions exists either to reduce or control the leakage and/or to take the leakage into account during the decision making process. At the design level, existing solutions to reduce leakage or to create low-leakage states are backward or forward body biasing, power partitioning and the use of built-in current monitoring. Solutions at the test application level, which take the leakage into account during decision-making, include using delta or relative IDDQ, current signatures/ ratios, IDDT, or combined IDDQ-IDDT tests. The main requirement for applying current testing to Nanotechnologies is the availability of tools that measure rapidly, have a wide range, a high resolution/repeatability, and real-time data processing capabilities to support advanced IDDQ test strategies and offer a true answer to remarks like: "Leakage currents surpassing defect current levels render IDDQ invalid.", "Wide leakage current variation across a production lot inhibits proper limit setting." and "The expected increase in parameter variability for nanotechnologies masks defect current visibility."Normal leakage, whether high or low, does not impact IDDQ application. The only requirements for proper IDDQ application are current stability at the selected measurement points and a repeatable test condition. If the test meets these conditions, -mostly the case-, application is unrestricted. Wide leakage variation imposes a burden on limit setting only if a single product-related limit is used. The use of data processing techniques such as Delta or relative IDDQ overcomes this. In addition, increasing design complexity results in a better matching of statedependent leakage. This results in a reduced IC-related vector-to-vector IDDQ variation, which at least partially or fully compensates for the increase in transistor-totransistor leakage variability in each new IC technology generation. Defect current v...

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Functional Constraints vs. Test Compression in Scan-Based Delay Testing

Polian

Fujiwara

2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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A practical evaluation of I/sub DDQ/ test strategies for deep submicron production test application. Experiences and targets from the field

Cited by 6 publications

References 12 publications

Delta-IDDQ Testing of Resistive Short Defects

Delta-IDDQ Testing of Resistive Short Defects

Current Testing for Nanotechnologies: A Demystifying Application Perspective.

Functional Constraints vs. Test Compression in Scan-Based Delay Testing

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