2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) 2017
DOI: 10.1109/async.2017.16
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A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines

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Cited by 10 publications
(1 citation statement)
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“…This will be later useful for interpreting the protocol impact on the circuit behavior when the Timed Petri Net model will be enriched in its SystemVerilog description. The approach can be generalized by considering communication channels, like joins, forks, splits, and merges when the pipeline structure is no longer linear [23]. In our method, the Timed Petri Net model is described in SystemVerilog.…”
Section: Timed Petri Net Modelmentioning
confidence: 99%
“…This will be later useful for interpreting the protocol impact on the circuit behavior when the Timed Petri Net model will be enriched in its SystemVerilog description. The approach can be generalized by considering communication channels, like joins, forks, splits, and merges when the pipeline structure is no longer linear [23]. In our method, the Timed Petri Net model is described in SystemVerilog.…”
Section: Timed Petri Net Modelmentioning
confidence: 99%