A Precision CMOS Amplifier Using Floating-Gate Transistors for Offset Cancellation

Srinivasan, Venkatesh; Serrano, G.; Gray, J.; Hasler, P.

doi:10.1109/jssc.2006.889365

Cited by 62 publications

(20 citation statements)

References 19 publications

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“…This is a kind of field programming method. In [7] and [11], a field programming method is used. In [7] the programming process requires several internal switches to perform the program function.…”

Section: Programming Circuit and Methodologymentioning

confidence: 99%

“…In [7] and [11], a field programming method is used. In [7] the programming process requires several internal switches to perform the program function. In this paper a programming method that utilizes indirect programming to avoid the use of internal switches is presented.…”

Section: Programming Circuit and Methodologymentioning

confidence: 99%

“…Another offset reduction technique used amplifiers is presented in [7]. This techniq trimming current sources that are connecte cascode output networks in order to equ when both amplifier inputs are at the same p…”

Section: A Floating-gate Current Source Trimmingmentioning

confidence: 99%

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Offset reduction in operational amplifiers using floating gate technology and LMS algorithm

Iglesias-Rojas

Gómez-Castañeda

Moreno-Cadenas

2011

2011 8th International Conference on Electrical Engineering, Computing Science and Automatic Control

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An offset reduction technique using floating gate technology and LMS algorithm is presented. Offset reduction in operational amplifiers is achieved by programming two floating gate transistors that form an important part of a single-stage folded cascode amplifier. Floating-gate transistors were programmed for a minimum offset voltage of ±25µV using 1.2µm CMOS process. Programmed operational amplifiers can be used in continuous-time operation for a long period of time without the need of reprogramming. Experimental results show that LMS algorithm can be used to program efficiently floatinggate transistor in order to reduce offset voltage in operational amplifiers.

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Section: Programming Circuit and Methodologymentioning

confidence: 99%

Section: Programming Circuit and Methodologymentioning

confidence: 99%

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Offset reduction in operational amplifiers using floating gate technology and LMS algorithm

Iglesias-Rojas

Gómez-Castañeda

Moreno-Cadenas

2011

2011 8th International Conference on Electrical Engineering, Computing Science and Automatic Control

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“…These techniques are typically limited to the order of 1-s timescales. Floating-Gate (FG) devices and circuits (e.g., [25]) have provided long-term memories for analog computation, enabling very precise programming of values (e.g., 14 bit [26]) for long-term lifetimes (e.g., [27,28]). Memory elements on the order of minutes or longer tend to be more challenging, but possible using adaptive FG techniques from ms to years [29,30], at reasonably low power, including in configurable spaces [31].…”

Section: Digital Computationmentioning

confidence: 99%

Starting Framework for Analog Numerical Analysis for Energy-Efficient Computing

Hasler

2017

JLPEA

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Abstract:The focus of this work is to develop a starting framework for analog numerical analysis and related algorithm questions. Digital computation is enabled by a framework developed over the last 80 years. Having an analog framework enables wider capability while giving the designer tools to make reasonable choices. Analog numerical analysis concerns computation on physical structures utilizing the real-valued representations of that physical system. This work starts the conversation of analog numerical analysis, including exploring the relevancy and need for this framework. A complexity framework based on computational strengths and weaknesses builds from addressing analog and digital numerical precision, as well as addresses analog and digital error propagation due to computation. The complimentary analog and digital computational techniques enable wider computational capabilities.

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“…Some of the most frequently used offset compensation techniques are layout techniques [4], trimming circuits [5][6][7][8], autozeroing, chopping, and ping-pong amplifiers [9][10][11][12][13] and use of digital-to-analog converters to adjust amplifier load currents [14]. However, those techniques do not fulfill all these requirements and/or affect the speed-accuracy-power tradeoff, among other additional disadvantages, as shown in Table 1.…”

Section: Introductionmentioning

confidence: 99%

New strategies to improve offset and the speed–accuracy–power tradeoff in CMOS amplifiers

Muñiz-Montero

Carvajal

Díaz-Sánchez

et al. 2007

Analog Integr Circ Sig Process

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Four continuous-time strategies to improve the speed-accuracy-power tradeoff in CMOS amplifiers by using low-power offset-compensation circuits are presented. The offset contribution at the output voltage is extracted and used to modify the DC component of the input voltage or the value of the active load, through low frequency feedback loops, which are realized using two transistors operating in weak inversion and a small capacitor. Because these circuits do not affect the bandwidth and allow using small transistors, the power consumption is greatly reduced with respect to an uncompensated amplifier of the same speed and offset behavior. The proposed strategies present reduced costs in area, power consumption and complexity, and a decrease in the low frequency noise contributions. MonteCarlo, HSPICE simulations results of common source, class AB and fully differential amplifiers, and experimental results of a class AB amplifier, all implemented in a 0.5-lm CMOS technology are shown. Statistical analyses of these strategies are also presented. Improvements up to 99.74% and 398.6% in the offset and the power consumption are respectively observed.

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A Precision CMOS Amplifier Using Floating-Gate Transistors for Offset Cancellation

Cited by 62 publications

References 19 publications

Offset reduction in operational amplifiers using floating gate technology and LMS algorithm

Offset reduction in operational amplifiers using floating gate technology and LMS algorithm

Starting Framework for Analog Numerical Analysis for Energy-Efficient Computing

New strategies to improve offset and the speed–accuracy–power tradeoff in CMOS amplifiers

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