A predictable and command-level priority-based DRAM controller for mixed-criticality systems

Kim, Hokeun; Bromany, David; Lee, Edward A.; Zimmer, M.; Shrivastava, Aviral; Oh, Junkwang

doi:10.1109/rtas.2015.7108455

Cited by 27 publications

(10 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Performance variability is a major concern for realtime systems because it complicates task scheduling. Conventional blocking DRAM refresh introduces a significant source of performance variability for real-time systems [7,26]. As such, applying Nonblocking Refresh to the memory systems of real-time systems also provides an added benefit of simplifying task scheduling.…”

Section: Generality Of Nonblocking Refreshmentioning

confidence: 99%

Nonblocking Memory Refresh

Nguyen

Lyu

Meng

et al. 2018

2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA)

View full text Add to dashboard Cite

Since its inception half a century ago, DRAM has required dynamic/active refresh operations that block read requests and decrease performance. We propose refreshing DRAM in the background without stalling read accesses to refreshing memory blocks, similar to the static/background refresh in SRAM. Our proposed Nonblocking Refresh works by refreshing a portion of the data in a memory block at a time and uses redundant data, such as Reed-Solomon codes, in the block to compute the block's refreshing/unreadable data to satisfy read requests. For proof of concept, we apply Nonblocking Refresh to server memory systems, where every memory block already contains redundant data to provide hardware failure protection. In this context, Nonblocking Refresh can utilize server memory system's existing per-block redundant data in the common-case when there are no hardware faults to correct, without requiring any dedicated redundant data of its own. Our evaluations show that on average across five server memory systems with different redundancy and failure protection strengths, Nonblocking Refresh improves performance by 16.2% and 30.3% for 16gb and 32gb DRAM chips, respectively. Nonblocking Memory RefreshKate Vy H Nguyen (GENERAL AUDIENCE ABSTRACT)Main memory is an essential component of computers, which stores data being actively used. The dominant type of computer main memory is Dynamic Random Access Memory (DRAM). DRAM is divided into thousands of memory cells. Each cell stores a single bit of data as a charge on a capacitor. Charges may leak over time, causing the data stored to be lost. To maintain the data stored in memory, DRAM must periodically restore charges held by memory cells through an operation known as memory refresh. Refresh operations decrease system performance because they stall read requests to refreshing memory blocks.A memory block refers to the unit of data transferred per memory request. Conventional memory systems refresh all the data within the block at a time, therefore the entire memory block is inaccessible while it is being refreshed. Our proposed Nonblocking Refresh reduces the amount of data in a memory block which is inaccessible due to refresh by refreshing only a portion the memory block at a time. To satisfy read requests, the block's refreshing/inaccessible data is computed using redundant data. Nonblocking Refresh improves DRAM performance by refreshing DRAM in the background without stalling read accesses to refreshing memory blocks. For proof of concept, we apply Nonblocking Refresh to server memory systems, where every memory block already contains redundant data to provide hardware failure protection. In this context, Nonblocking Refresh can utilize server memory system's existing redundant data to improve performance, without adding additional redundancy overhead. Our evaluations show that on average across five server memory systems with different redundancy and failure protection strengths, Nonblocking Refresh improves performance by 16%-30%.

show abstract

Section: Generality Of Nonblocking Refreshmentioning

confidence: 99%

Nonblocking Memory Refresh

Nguyen

Lyu

Meng

et al. 2018

2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA)

View full text Add to dashboard Cite

show abstract

“…Full temporal isolation can be achieved with the hard-real-time threads of PRET [57]. Predictable memory access time can be guaranteed through a DRAM controller with hardware-supported command-level prioritization [58].…”

Section: Logical Clocks and Real Timementioning

confidence: 99%

On Enabling Technologies for the Internet of Important Things

et al. 2019

Self Cite

View full text Add to dashboard Cite

The Internet of Things leverages Internet technology in cyber-physical systems (CPSs), but the protocols and principles of the Internet were designed for interacting with information systems, not cyberphysical systems. For one, timeliness is not a factor in any widespread Internet technology, with qualityof-service features having been routinely omitted for decades. In addition, for things, safety, freedom from physical harm, is even more important than information security, the focus on the Internet. Nevertheless, properties of the Internet are valuable in CPSs, including a global namespace, reliable (eventual) delivery of messages, end-to-end security through asymmetric encryption, certificate-based authentication, and the ability to aggregate data from a multiplicity of sources in the cloud. This paper discusses and surveys architectural approaches, communication protocols, and programming models that promise to bridge the gap, enabling the use of the Internet technologies even in safety-critical, cyber-physical applications such as factory automation and transportation. Specifically, we argue that smart gateways hosted on edge computers complement cloud-based services; they can provide tighter control over timing and security that is robust against network outages, play an active role in managing interactions between things, and isolate safetycritical services from best-effort services. We explain how time sensitive network technology can be leveraged to reliably orchestrate a multiplicity of things, and how augmenting our programming models with a well-defined notion of time can make systems more deterministic and more testable.

show abstract

“…In-memory computing technology has grown rapidly, to adapt to changing needs of businesses. A growing number of in-memory applications have gained popularity in recent years, for example, the database Redis [1], the key-value store Memcached [2], the computing framework Spark [3], and others [4]. These applications and their quality of services will generate a large number of mission-critical workloads that frequently access memory or cache [5], [6], [7].…”

Section: Introductionmentioning

confidence: 99%