A Preliminary Empirical Study of the Power Efficiency of Matrix Multiplication

Abstract

Matrix multiplication is ubiquitous in high-performance applications. It will be a significant part of exascale workloads where power is a big concern. This work experimentally studied the power efficiency of three matrix multiplication algorithms: the definition-based, Strassen’s divide-and-conquer, and an optimized divide-and-conquer. The study used reliable on-chip integrated voltage regulators for measuring the power. Interactions with memory, mainly cache misses, were thoroughly investigated. The main result was that the optimized divide-and-conquer algorithm, which is the most time-efficient, was also the most power-efficient, but only for cases that fit in the cache. It consumed drastically less overall energy than the other two methods, regardless of placement in memory. For matrix sizes that caused a spill to the main memory, the definition-based algorithm consumes less power than the divide-and-conquer ones at a high total energy cost. The findings from this study may be of interest when cutting power usage is more vital than running for the shortest possible time or least amount of energy.

Investigation of Energy and Power Characteristics of Various Matrix Multiplication Algorithms

“…The methodology used in this study was based on the established techniques for experimental measurement of energy and power on modern CPU platforms that were developed by some of the authors of this report and detailed in [22,24]. The main difference was the shift to another CPU platform.…”

“…Jammal et al [22] compared the energy performance of a definition-based algorithm against two basic divide-and-conquer ones on an HPC-class Haswell Intel processor. They showed that the divide-and-conquer algorithms were the best in terms of power and energy consumption when the calculations fit in the cache.…”

“…Jammal et al [22] 2023 Conducted a preliminary empirical evaluation of the power efficiency of basic matrix multiplication algorithms.…”

“…In [22], the authors commented on how much power these seemingly fundamental computations consumed on an HPC-class Intel Haswell CPU from 2014: as much as 80 watts at matrix size 1500. The AMD EPYC, a later CPU (2021), consumed 20 and 14 watts for DEF and STRAS, respectively, for the same size matrix.…”

An Experimental Approach to Estimation of the Energy Cost of Dynamic Branch Prediction in an Intel High-Performance Processor

“…Jammal et al [18] studied the power efficiency of three matrix multiplication algorithms, i.e., definition-based, Strassen's divide-and-conquer, and improved divide-andconquer, on the Intel Xeon CPU E5-2680. The main finding of this work is that the fastest divide-and-conquer algorithm is power-efficient only for small matrix sizes.…”