A PRET architecture supporting concurrent programs with composable timing properties

Liu, Isaac; Reineke, Jan; Lee, Edward A.

doi:10.1109/acssc.2010.5757922

Cited by 56 publications

(38 citation statements)

References 24 publications

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“…Our design can be seen as an instance of the PRET architecture [11]. However, we leave the name PRET to the original Berkeley design.…”

Section: Related Workmentioning

confidence: 99%

Time-predictable chip-multiprocessor design

Schoeberl

2010

2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers

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Abstract-Real-time systems need time-predictable platforms to enable static worst-case execution time (WCET) analysis. Improving the processor performance with superscalar techniques makes static WCET analysis practically impossible. However, most real-time systems are multi-threaded applications and performance can be improved by using several processor cores on a single chip. In this paper we present a time-predictable chipmultiprocessor system that aims to improve system performance while still enabling WCET analysis.The proposed chip-multiprocessor (CMP) uses a shared memory with a time-division multiple access (TDMA) based memory access scheduling. The static TDMA schedule can be integrated into the WCET analysis. Experiments with a JOP based CMP showed that the memory access starts to dominate the execution time when using more than 4 processor cores. To provide a better scalability, more local memories have to be used. We add a processor local scratchpad memory and split data caches, which are still time-predictable, to the processor cores.

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“…Our design can be seen as an instance of the PRET architecture [11]. However, we leave the name PRET to the original Berkeley design.…”

Section: Related Workmentioning

confidence: 99%

Time-predictable chip-multiprocessor design

Schoeberl

2010

2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers

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“…Then, the algorithm creates a new vertex with either T EXT or T EN T attributes for the instruction ci. We then add both the vertices to L V (lines 8,14), and build the sequence of instructions L I by adding the instruction in each iteration (line 17) until we encounter a timing instruction (lines 9, 15). For example, if the vertex has exactly one set time (or delay until ), it will be split into three vertices, {v 1 , v 2 , v 3 }.…”

Section: Identifying Timed Blocksmentioning

confidence: 99%

An instruction scratchpad memory allocation for the precision timed architecture

Prakash¹,

Patel²

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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This work presents a static instruction allocation scheme for the precision timed architectures (PRET) scratchpad memory. Since PRET provides timing instructions to control the temporal execution of programs, the objective of the allocation scheme is to ensure that the explicitly specified temporal requirements are met. Furthermore, this allocation incorporates instructions from multiple hardware threads of the PRET architecture. We formulate the allocation as an integerlinear programming problem, and we implement a tool that takes binaries, constructs a controlflow graph, performs the allocation, rewrites the binary with the new allocation, and generates an output binary for the PRET architecture. We carry out experiments on a modified version of the Malardalen benchmarks to illustrate that commonly known ACET and WCET based approaches cannot be directly applied to meet explicit timing requirements. We also show the advantage of performing the allocation across multiple threads. We present a real time benchmark controlling an Unmanned Air Vehicle as the case study.iii

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“…The precision timed (PRET) architecture is first presented in [8]. PRET implements a RISC pipeline and performs chiplevel multithreading for several threads to eliminate data forwarding and branch prediction [11]. The first FPGA version of PRET implements the ARM instruction set [9], [10].…”

Section: Related Workmentioning

confidence: 99%

A time-predictable stack cache

Abbaspour

Brandner²,

Schoeberl³

2013

16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC 2013)

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Abstract-Real-time systems need time-predictable architectures to support static worst-case execution time (WCET) analysis. One architectural feature, the data cache, is hard to analyze when different data areas (e.g., heap allocated and stack allocated data) share the same cache. This sharing leads to less precise results of the cache analysis part of the WCET analysis.Splitting the data cache for different data areas enables composable data cache analysis. The WCET analysis tool can analyze the accesses to these different data areas independently.In this paper we present the design and implementation of a cache for stack allocated data. Our port of the LLVM C++ compiler supports the management of the stack cache. The combination of stack cache instructions and the hardware implementation of the stack cache is a further step towards timepredictable architectures.

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A PRET architecture supporting concurrent programs with composable timing properties

Cited by 56 publications

References 24 publications

Time-predictable chip-multiprocessor design

Time-predictable chip-multiprocessor design

An instruction scratchpad memory allocation for the precision timed architecture

A time-predictable stack cache

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