A PRET microarchitecture implementation with repeatable timing and competitive performance

Liu, Isaac; Reineke, Jan; Broman, David; Zimmer, M.; Lee, Edward A.

doi:10.1109/iccd.2012.6378622

Cited by 73 publications

(56 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This approach enables the analysis of tasks in isolation since the interference on other tasks can be conservatively accounted for using this bound on the latency of each access. Similarly, the PTARM (Liu et al 2012) enforces constant latencies for all instructions, including loads and stores; however, both cases represent customized hardware. Lv et al (2010) used timed automata to model the memory bus and the memory request patterns.…”

Section: Related Work With a Focus On The Memory Busmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

Self Cite

View full text Add to dashboard Cite

In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on contextindependent WCET values. Instead, the analysis formulates response times directly The additional material includes: Section 4: analysis for warmed-up caches and dynamic scratchpads (Sects. 4.3 and 4.2). Section 7: extensions to the task model, including RTOS and interrupts, shared software resources, and open systems and incremental verification. Section 8: presentation of a cycle-accurate multicore simulator. Section 9: evaluation of different local memory types (Sect. 9.2), a comparison between predictable and reference architectures (Sect. 9.3), and a verification of the precision of the analysis using results from the simulator (Sect. 9.4). 123Real-Time Syst from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.

show abstract

Section: Related Work With a Focus On The Memory Busmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

Self Cite

View full text Add to dashboard Cite

show abstract

“…Work along these lines includes classifications of existing microarchitectures in terms of their predictability [17], [20], studies of the predictability of caches [6], and proposals of new microarchitectural techniques, such as novel multithreaded architectures that eliminate interference between threads [21], [22], [23], [24], [25] and DRAM controllers that allow multiple tasks to share DRAM devices in a predictable and composable fashion [26], [27]. In the following, we review work specifically concerning the interplay between multitasking and the memory hierarchy.…”

Section: Related Workmentioning

confidence: 99%

Selfish-LRU: Preemption-aware caching for predictability and performance

Reineke

Altmeyer

Grund

et al. 2014

2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

Self Cite

View full text Add to dashboard Cite

Abstract-We introduce Selfish-LRU, a variant of the LRU (least recently used) cache replacement policy that improves performance and predictability in preemptive scheduling scenarios.In multitasking systems with conventional caches, a single memory access by a preempting task can trigger a chain reaction leading to a large number of additional cache misses in the preempted task. Selfish-LRU prevents such chain reactions by first evicting cache blocks that do not belong to the currently active task. Simulations confirm that Selfish-LRU reduces the CRPD (cache-related preemption delay) as well as the overall number of cache misses. At the same time, it simplifies CRPD analysis and results in smaller CRPD bounds.

show abstract

“…PRET implements a RISC pipeline and performs chiplevel multithreading for several threads to eliminate data forwarding and branch prediction [11]. The first FPGA version of PRET implements the ARM instruction set [9], [10]. Current work is ongoing to implement a PRET processor with the RISC-V [26] instruction set and to allow a variable number of hardware threads.…”

Section: Related Workmentioning

confidence: 99%

A time-predictable stack cache

Abbaspour

Brandner²,

Schoeberl³

2013

16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC 2013)

View full text Add to dashboard Cite

Abstract-Real-time systems need time-predictable architectures to support static worst-case execution time (WCET) analysis. One architectural feature, the data cache, is hard to analyze when different data areas (e.g., heap allocated and stack allocated data) share the same cache. This sharing leads to less precise results of the cache analysis part of the WCET analysis.Splitting the data cache for different data areas enables composable data cache analysis. The WCET analysis tool can analyze the accesses to these different data areas independently.In this paper we present the design and implementation of a cache for stack allocated data. Our port of the LLVM C++ compiler supports the management of the stack cache. The combination of stack cache instructions and the hardware implementation of the stack cache is a further step towards timepredictable architectures.

show abstract

A PRET microarchitecture implementation with repeatable timing and competitive performance

Cited by 73 publications

References 23 publications

An extensible framework for multicore response time analysis

An extensible framework for multicore response time analysis

Selfish-LRU: Preemption-aware caching for predictability and performance

A time-predictable stack cache

Contact Info

Product

Resources

About