A Probabilistic-Based Design for Nanoscale Computation

Bahar, R. Iris; Chen, Jie; Mundy, Joseph L.

doi:10.1007/1-4020-8068-9_5

Cited by 35 publications

(23 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In order to tackle this issue, a number of different approaches have been reported in literature, including probabilistic transfer matrix (PTM) method [10][11][12], Bayesian networks (BN) [13][14][15], Markov random field (MRF) [16][17][18][19][20], Monte Carlo (MC) simulation, testing-based method [3], stochastic computation model (SCM) [2,21], probabilistic gate model (PGM) [22][23][24][25], observability-based analysis [26], Boolean difference-based error calculator (BDEC), and correlation coefficient method-(CCM-) based approaches [8,[26][27][28]. In the following, we overview some of these approaches and analyze their pros and cons in terms of accuracy, efficiency, and flexibility with simulation results.…”

Section: Complexity Of Gate-level Reliability Analysismentioning

confidence: 99%

Gate-Level Circuit Reliability Analysis: A Survey

Xiao

Chen

2014

VLSI Design

View full text Add to dashboard Cite

Circuit reliability has become a growing concern in today's nanoelectronics, which motivates strong research interest over the years in reliability analysis and reliability-oriented circuit design. While quite a few approaches for circuit reliability analysis have been reported, there is a lack of comparative studies on their pros and cons in terms of both accuracy and efficiency. This paper provides an overview of some typical methods for reliability analysis with focus on gate-level circuits, large or small, with or without reconvergent fanouts. It is intended to help the readers gain an insight into the reliability issues, and their complexity as well as optional solutions. Understanding the reliability analysis is also a first step towards advanced circuit designs for improved reliability in the future research.

show abstract

Section: Complexity Of Gate-level Reliability Analysismentioning

confidence: 99%

Gate-Level Circuit Reliability Analysis: A Survey

Xiao

Chen

2014

VLSI Design

View full text Add to dashboard Cite

show abstract

“…This probability will be conditioned on F i being '1', so we denote this as F k 1 where F k 1 P(F k =1|F i =1). Then we set F k to '1' and find the signal probability at F i 's POC, which we denote as Z 1,1 . Next, F k is set to '0' and we calculate the POC value Z 1,0 .…”

Section: An Accurate Reliability Modelmentioning

confidence: 99%

“…This concern for the reliability of nanoelectronics has motivated efforts to develop reliability evaluation techniques based on the probabilistic nature of future nanoscale computation [1,2,3]. This paper contributes to this work by developing a method for accurately and efficiently evaluating reliability at the logic-gate level.…”

Section: Introductionmentioning

confidence: 99%

Towards Accurate and Efficient Reliability Modeling of Nanoelectronic Circuits

Taylor

Han²,

Fortes³

2006

2006 Sixth IEEE Conference on Nanotechnology

View full text Add to dashboard Cite

-The emergence of nanoelectronic devices which rely on fundamentally unreliable physics calls for reliability evaluation techniques and practical design-for-reliability solutions. This paper reviews a method that uses probabilistic gate models (PGMs) for reliability estimation and improves upon this method to enable the accurate evaluation of reliabilities of circuits. When applied to large, complex circuits, however, this and other accurate methods lead to long execution times. To simplify reliability analysis, this paper leverages the fact that many large circuits consist of common logic modules. The overall circuit reliability estimation can be made on the basis of accurate PGM-based reliabilities of individual modules. This technique significantly reduces the PGM method's complexity, making it suitable for practical design-for-reliability applications. Results from the use of this technique on benchmark circuits indicate that the estimates produced correctly identify the most vulnerable paths through a circuit.

show abstract

“…We employ two simple rules from the notion of Boolean ring, as used in the MRF method [4]. These rules relate the Boolean logic variables and the algebraic operations of their probabilities:…”

Section: Probabilistic Models For Logic Gatesmentioning

confidence: 99%

“…Analytical approaches using Markov chains [3], Markov random fields (MRF) [4], bifurcation analysis [5] and probabilistic transfer matrices (PTMs) [6] have been proposed for the evaluation of circuit reliability. In this paper, we review our recent work on probabilistic methods for obtaining error bounds and reliability estimates of nanoelectronic circuits.…”

Section: Introductionmentioning

confidence: 99%