A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model

Abstract

Our aim is the development of a novel probabilistic method to estimate the power consumption of a combinational circuit under real gate delay model handling temporal, structural and input pattern dependencies. The chosen gate delay model allows handling both the functional and spurious transitions. It is proved that the switching activity evaluation problem assuming real gate delay model is reduced to the zero delay switching activity evaluation problem at specific time instances. A modified Boolean function, which describes the logic behavior of a signal at any time instance, including time parameter is introduced. Moreover, a mathematical model based on Markov stochastic processes, which describes the temporal and spatial correlation in terms of the associated zero delay based parameters is presented. Based on the mathematical model and considering the modified Boolean function, a new algorithm to evaluate the switching activity at specific time instances using Ordering Binary Decision Diagrams (OBBDs) is also presented. Comparative study of benchmark circuits demonstrates the accuracy and efficiency of the proposed method.

Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

“…Application of this deterministic technique presented here along with the probabilistic method (which change logical inputs) assures considerable additional reduction in power dissipation irrespective of the input signal pattern. In addition, taking into account the data correlations of the input streams [10,11] further enhancements of the transistor reordering can be achieved for the dynamic BiCMOS logic gates. Improvements in the delay-time has also been achieved in the process, resulting in considerable enhancement of the power-delay product figure-of-merit.…”

Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model

“…The average dynamic power can be expressed as a function of the circuit parameters as follows [10] : where V dd is the source supply voltage, N is the total number of nodes, T is the clock cycle period, C i is the load capacitance of node i and α i is the toggle rate of node i , i.e., the rate of the transitions between zeros and ones occurring at node i . V dd and C i depend on the device fabrication and T depends on the circuit application specifications while α i is the only parameter in the equation that depends on the circuit operation; therefore, its value is a sufficient indicator of the average dynamic power of the circuit [1] .…”

“…Power consumption is an essential factor in digital VLSI circuits. High power consumption affects circuit reliability and can cause runtime errors or shorten circuit lifetime [1] . Many power estimation methods have been developed; they can mainly be divided into two main categories.…”

“…In this paper, a deterministic method to calculate the average power consumption for digital CMOS circuits is described at the gate level. The method uses a real-delay model, where different gate types have different delays [1] ; this may lead to inevitable glitches and in turn increases the power consumption [10] .…”