A Probabilistic Prediction-Based Fixed-Width Booth Multiplier for Approximate Computing

He, Yajuan; Yi, Xilin; Zhang, Ziji; Ma, Baosong; Li, Qiang

doi:10.1109/tcsi.2020.3001654

Cited by 19 publications

(4 citation statements)

References 20 publications

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“…Less space means the multiplier can work more efficiently, which is a good thing. One issue, nevertheless, does exist [14]. Both the bit size and the area increase with increasing values.…”

Section: IIImentioning

confidence: 99%

Design Wallace Tree Multiplier Using Reversible Gates

Kishore,

Prakash,

Sachin

et al. 2024

IJRASET

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Multipliers are essential components in digital circuit design. They have wide spread applications in digital signal processing and communication systems. Circuit designers in VLSI design seek compact, small scale circuits with low power consumption and minimal delay. The Wallace tree multiplier is an advanced version of tree based multipliers. Numerous algorithms have been developed to create the fastest multipliers, and the Wallace tree multiplier is one such example. It utilizes reversible compressors, full adders, and half adders. The results demonstrate that the Wallace tree multiplier using reversible gates outperforms traditional multipliers in terms of power dissipation and delay, with values of 0.027W and 29.327nS respectively.

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“…Less space means the multiplier can work more efficiently, which is a good thing. One issue, nevertheless, does exist [14]. Both the bit size and the area increase with increasing values.…”

Section: IIImentioning

confidence: 99%

Design Wallace Tree Multiplier Using Reversible Gates

Kishore,

Prakash,

Sachin

et al. 2024

IJRASET

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“…At circuit level, research has mostly focused on decreasing circuit complexity (so reducing the number of transistors) by introducing acceptable errors in computational units (such as adders and multipliers) to improve performance (in particular, delay and energy) [10][11][12][13][14]. At logic level, [15,16] have utilized specialized simulation frameworks to realize different approximate multipliers. An energy-efficient fixed-width Booth multiplier based on probabilistic prediction has been presented in [15] by introducing an error compensation circuit and analyzing probabilistically the partial products as per Booth encoding; approximate compressors based on AND-OR gates [16] have been proposed and applied to the lesssignificant part of a partial product of multipliers to decrease the error rate.…”

Section: Introductionmentioning

confidence: 99%

“…At logic level, [15,16] have utilized specialized simulation frameworks to realize different approximate multipliers. An energy-efficient fixed-width Booth multiplier based on probabilistic prediction has been presented in [15] by introducing an error compensation circuit and analyzing probabilistically the partial products as per Booth encoding; approximate compressors based on AND-OR gates [16] have been proposed and applied to the lesssignificant part of a partial product of multipliers to decrease the error rate. Approximate Booth multipliers have been proposed in [17] by employing modified radix-4 booth encoding designs.…”

Section: Introductionmentioning

confidence: 99%

On the Commutative Operation of Approximate CMOS Ripple Carry Adders (RCAs)

Huang¹,

Thulasiraman²,

Almurib³

et al. 2022

Preprint

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<p>Approximate cells can be used to design Ripple Carry Adders (RCAs) for realizing approximate addition in energy-efficient CMOS digital circuits. As inputs of approximate cells could be non-commutative in nature, approximate adders may show different output values under a commutative operation, and this may have a significant effect on the generated sum. This paper presents a detailed analysis of the commutative addition in RCAs made of different approximate cells. Initially, the impact of a non-commutative addition (NCA) to RCAs by approximate cells is assessed by exhaustive simulation at adder level. The results show that at most 17% of additions executed using AFA3 suffer from the non-commutative property, while the values for other adder cells can reach 75%~99%. Then, an extensive analysis using images from a publicly available library is performed by comparing three-image additions with two-image additions. As a further evaluation, the adders are assessed in an image denoising application. As expected, the effect of NCA is especially pronounced for some non-commutative adders, such as AA2 and AMA4. NCA is also cumulative with the number of approximate additions, thereby causing a significant variation in the output image quality. In terms of metrics, the largest average difference in mean error distance (DMED) for three-image addition is 5.3 times higher than for two-image addition. Rankings of the non-commutative approximate adders show that AMA3 and AFA1 based adders are the best schemes with respect to commutative addition; they both also show good performance in image denoising.</p>

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“…However, the setup time for some part of the circuit is required in these hybrid methods. Recently, the great demand of high‐performance FWBM arises because of the wide applications of approximate computing (AC) 22,23 . Due to the huge amount of computation units, the area and power efficiency of FWBM have become the main concerns 24‐26 …”

Section: Introductionmentioning

confidence: 99%

Simple and hardware‐efficient row‐based direct‐mapping estimators in fixed‐width modified Booth multipliers

Chen

Lai

et al. 2021

Circuit Theory & Apps

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Summary The great demand of high‐performance fixed‐width two's‐complement modified Booth multipliers (FWBM) arises because of the wide applications of approximate computing. In this paper, a row‐based direct‐mapping (RDM) method for designing error estimators in FWBM is proposed. The proposed closed form is derived from probability summation of each entire row to avoid the long setup time of exhaustive simulations. Consequently, a simple and systematic procedure by the Karnaugh map can be utilized to design low‐error and hardware‐efficient compensation circuits for various widths of FWBMs. By checking the leading column of the truncation part, the extendable design principle can be easily applied to different lengths and different columns inspected. We use Synopsys Design Compiler and TSMC 90 nm standard cell library to synthesize the register transfer language (RTL) design of our proposed estimators. In addition, the RDM is synthesized using the Xilinx Vivado tool with Xilinx Kintex‐7 XC7K325T‐2FFG900C FPGA. Results of software simulation, hardware synthesis, and implementation experiment validate the high accuracy, hardware saving, and power efficiency of the proposed RDM estimators.

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A Probabilistic Prediction-Based Fixed-Width Booth Multiplier for Approximate Computing

Cited by 19 publications

References 20 publications

Design Wallace Tree Multiplier Using Reversible Gates

Design Wallace Tree Multiplier Using Reversible Gates

On the Commutative Operation of Approximate CMOS Ripple Carry Adders (RCAs)

Simple and hardware‐efficient row‐based direct‐mapping estimators in fixed‐width modified Booth multipliers

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