A Process and Data Variations Tolerant Capacitive Coupled 10T1C SRAM for In-Memory Compute (IMC) in Deep Neural Network Accelerators

Iqbal, Belal; Grover, Anuj; Rawat, Harsh

doi:10.1109/aicas54282.2022.9870026

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A Process and Data Variations Tolerant Capacitive Coupled 10T1C SRAM for In-Memory Compute (IMC) in Deep Neural Network Accelerators

Cited by 5 publications

References 11 publications

Robust and High-Performance Digital In-Memory Computing in 5T Gain Cell Embedded DRAM

Robust and High-Performance Digital In-Memory Computing in 5T Gain Cell Embedded DRAM

Word Line Underdrive Technique to Increase Signal Swing and Linearity for In-Memory Compute Applications (IMC) in 65nm LSTP technology

Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network

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