A programmable CMOS voltage reference based on a proportional summing circuit

Abstract

This paper describes a new approach for design and implementation of programmable voltage reference based on current mode bandgap voltage reference and a proportional summing circuit. The circuit is simulated and fabricated with Chartered 0.35um mixed-signal technology, and our measurements demonstrate that its temperature coefficient is ±35.07ppm/°C from 0 to 100°C.The supply voltage is varied from 2.7-5V and the varied voltage reference is about 5mV. Depending on the state of the five VID inputs, an output voltage between 1.075V and 1.85V is programmed in 25mV increments.

A low-power, small-area voltage reference array for a wafer-scale prototyping platform

“…Half of this area is used by the beta-multiplier and start-up circuitry (BM-SU) and the other half by the programmable reference array (PRA). Its area is at least one order of magnitude smaller than that proposed by Zhang et al [3] (Tab. I), which was implemented in 0.35µm CMOS technology.…”

“…The programmability can be achieved using a DAC coupled with a bandgap reference voltage using PNP parasitic vertical diode but the silicon area is prohibitive. For example, the circuit proposed by Zhang et al [3] occupies 0.111 mm 2 and is twenty times larger than the available area budget. Others have proposed to use first order delta-sigma modulator to modulate a voltage reference [4], or a variable voltage reference using a feedback control technique to get very low temperature drifting [5], but their areas and power consumptions are too large considering the physical layout constraints of the WaferIC TM .…”