1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers 1985
DOI: 10.1109/isscc.1985.1156829
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A programmable digital signal processor with 32b floating point arithmetic

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Cited by 18 publications
(11 citation statements)
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“…(2) and (3) can be simplified further when the detection is restricted to only leading zeros or leading ones. For example, when the circuit for detection of leading zeros does not need to consider cases where leading ones might result, then the leading zero indicator can be simplified to Further simplification results for a case which is even more restricted, as described in [8J and [SI.…”
Section: Detection Of First Leading Digit --Restricted Casesmentioning
confidence: 99%
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“…(2) and (3) can be simplified further when the detection is restricted to only leading zeros or leading ones. For example, when the circuit for detection of leading zeros does not need to consider cases where leading ones might result, then the leading zero indicator can be simplified to Further simplification results for a case which is even more restricted, as described in [8J and [SI.…”
Section: Detection Of First Leading Digit --Restricted Casesmentioning
confidence: 99%
“…(1) is referred to as Kershaw, (the earliest reference), the LZA described by equ. (2) and (3) is referred to as Schmookler, and the LZA described by equ. (4) and (5) is referred to as Britton. Only Kershaw and Schmookler cover both leading zeros and ones, without using any carry signals from the adder.…”
Section: Comparing Cost and Delaymentioning
confidence: 99%
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