A programmable dynamic interconnection network router with hidden refresh

Abstract

Abstract-A VLSI implementation of a programmable pipelined router scheme for parallel machine interconnection networks is presented in this paper. The implementation is based on a dynamic content-addressable memory (DCAM) that supports unique bit masking per entry. The number of required DCAM entries is extremely small; it is of the same order as the node degree (output ports). This, in turn, makes it possible to implement a dynamic content-addressable memory in order to reduce the physical size of the system. A DCAM is implemented with only six and a half transistors (one transistor is shared by two cells). We have provided circuitry and arranged timing to achieve refreshing of the stored data in a hidden fashion. In addition to the DCAM, we have incorporated a fast priority scheme that allows only one entry to be selected. The router executes routing algorithms in 1.5 clock cycles, this being the fastest approach for flexible routers. The prototype router has 24 entries, and is able to sustain a throughput of one routing decision per cycle.Index Terms-Content addressable memory, dynamic circuits, matching with ternary digits, parallel comparison, pipelining, routing algorithm execution, ternary digit logic.

Decoupled dynamic ternary content addressable memories

“…A CAM performs a parallel comparison of stored data with an input argument. These features have earned CAM's widespread usage which include: translation look-aside buffers for virtual memory systems, tag directories in fully associative cache organizations [1], collision detection VLSI processor for intelligent vehicles [2], interconnection network router [3], [4], database accelerator [5], self-testing reconfigurable CAM [6], and applications in artificial intelligence and image processing. Additional applications include logic inference, classifiers [7], [8], pattern matching [9], sorting [10], and applications that require searches in specific address ranges [11].…”

“…A don't care state can be used to mask off some bits in a memory location and also during match function. Table I shows a ternary CAM application for routing tables [3]. In this application, a hypercube tree routing algorithm is encoded in the CAM using ternary values.…”

A hybrid wave-pipelined network router

“…The BPAR supports three basic operation modes: Normal or matching, programming or data loading and refreshing [3]. In normal mode the previously loaded data is compared to data presented at the search argument register and the results passed to the selection function.…”

“…The DRAM structure is able to perform an OR function per column when multiple RAM rows are selected; this is when multiple matches are passed on. The DRAM structure is explained in [3].…”

Self-timed refreshing approach for dynamic memories

“…In our approach once the refreshing process starts, it continues until the entire memory array is refreshed. This process however should be made transparent (or hidden) to other memory modes of operation [6], [7].…”