A Programmable Event-driven Architecture for Evaluating Spiking Neural Networks

Venkataramani, Swagath; Gala, Neel; Sen, Sanchari; Kamakoti, V.; Raghunathan, Anand

doi:10.1109/islped.2017.8009176

Cited by 20 publications

(13 citation statements)

References 12 publications

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“…They allow organizing the sequence of upstream spikes to be delivered to downstream neurocores in order to reduce potential redundant memory accesses. Roy et al [153] also interestingly share them between several neurocores. This may maximize the efficiency of topology mapping, for instance by allowing a single spike scheduler per SNN layer, even for networks with large layers.…”

Section: Core Organization For Low Power Spiking Neural Network Evalumentioning

confidence: 87%

“…Reported digital designs usually employ a single PE which updates every neurons mapped to the core [28,34,38,122,130,153,167,193,194]. For each algorithmic time step, the neurocore runs through the following procedure: first, every upstream spikes received during the previous time step, which are stored in an event queue such as spike schedulers [153,193] or FIFO registers [28,115], are processed sequentially. Each spike is an address which allows to identify the downstream neurons according to the connection map of the part of the SNN processed by the neurocore.…”

Section: Core Organization For Low Power Spiking Neural Network Evalumentioning

confidence: 99%

“…The synchronous operation but asynchronous communication between neurocores requires the presence of event queues to receive the incoming spikes asynchronously during an algorithmic time step. As such, spike schedulers [153,193] are powerful tools. They allow organizing the sequence of upstream spikes to be delivered to downstream neurocores in order to reduce potential redundant memory accesses.…”

Section: Core Organization For Low Power Spiking Neural Network Evalumentioning

confidence: 99%

“…Finally, the AER protocol is compatible with various NoC routing architectures and broadcast schemes, such as 2D mesh [38,49,122], multicast tree [15], or systolic ring [91,96,153]. It is thus possible for the hardware designer to adapt the routing scheme employed to best fit the requirements of the accelerator.…”

Section: Reduced Communication Costmentioning

confidence: 99%

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Spiking Neural Networks Hardware Implementations and Challenges

Bouvier

Valentian

Mesquida

et al. 2019

J. Emerg. Technol. Comput. Syst.

197

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Neuromorphic computing is henceforth a major research field for both academic and industrial actors. As opposed to Von Neumann machines, brain-inspired processors aim at bringing closer the memory and the computational elements to efficiently evaluate machine-learning algorithms. Recently, Spiking Neural Networks, a generation of cognitive algorithms employing computational primitives mimicking neuron and synapse operational principles, have become an important part of deep learning. They are expected to improve the computational performance and efficiency of neural networks, but are best suited for hardware able to support their temporal dynamics. In this survey, we present the state of the art of hardware implementations of spiking neural networks and the current trends in algorithm elaboration from model selection to training mechanisms. The scope of existing solutions is extensive; we thus present the general framework and study on a case-by-case basis the relevant particularities. We describe the strategies employed to leverage the characteristics of these event-driven algorithms at the hardware level and discuss their related advantages and challenges.

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Section: Core Organization For Low Power Spiking Neural Network Evalumentioning

confidence: 87%

Section: Core Organization For Low Power Spiking Neural Network Evalumentioning

confidence: 99%

Section: Core Organization For Low Power Spiking Neural Network Evalumentioning

confidence: 99%

Section: Reduced Communication Costmentioning

confidence: 99%

See 2 more Smart Citations

Spiking Neural Networks Hardware Implementations and Challenges

Bouvier

Valentian

Mesquida

et al. 2019

J. Emerg. Technol. Comput. Syst.

197

View full text Add to dashboard Cite

show abstract

“…Due to these differences, SNNs are not well-suited to commodity hardware platforms like graphics processing units (GPUs). Further, in contrast to hardware accelerators for ANNs, which usually focus on exploiting regular data parallelism, hardware architectures for spiking networks (e.g., Furber et al, 2014;Neil and Liu, 2014;Akopyan et al, 2015;Roy et al, 2017) focus more on features that enable efficient eventdriven computation.…”

Section: Introductionmentioning

confidence: 99%

Probabilistic Spike Propagation for Efficient Hardware Implementation of Spiking Neural Networks

et al. 2021

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Spiking neural networks (SNNs) have gained considerable attention in recent years due to their ability to model temporal event streams, be trained using unsupervised learning rules, and be realized on low-power event-driven hardware. Notwithstanding the intrinsic desirable attributes of SNNs, there is a need to further optimize their computational efficiency to enable their deployment in highly resource-constrained systems. The complexity of evaluating an SNN is strongly correlated to the spiking activity in the network, and can be measured in terms of a fundamental unit of computation, viz. spike propagation along a synapse from a single source neuron to a single target neuron. We propose probabilistic spike propagation, an approach to optimize rate-coded SNNs by interpreting synaptic weights as probabilities, and utilizing these probabilities to regulate spike propagation. The approach results in 2.4–3.69× reduction in spikes propagated, leading to reduced time and energy consumption. We propose Probabilistic Spiking Neural Network Application Processor (P-SNNAP), a specialized SNN accelerator with support for probabilistic spike propagation. Our evaluations across a suite of benchmark SNNs demonstrate that probabilistic spike propagation results in 1.39–2× energy reduction with simultaneous speedups of 1.16–1.62× compared to the traditional model of SNN evaluation.

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