A programmable gain amplifier with a DC offset calibration loop for a direct-conversion WLAN transceiver

A differential automatic gain control (AGC) circuit is presented. The AGC architecture contains twostage variable gain amplifiers (VGAs) which are implemented with a Gilbert cell, a peak detector (PD), a low pass filter, an operational amplifier, and two voltage to current (V -I ) convertors. One stage VGA achieves 30 dB gain due to the use of active load. The AGC circuit is implemented in UMC 0.18-m single-poly six-metal CMOS process technology. Measurement results show that the final differential output swing of the 2nd stage VGA is about 0.9-Vpp; the total gain of the two VGAs can be varied linearly from -10 to 50 dB when the control voltage varies from 0.3 to 0.9 V. The final circuit (containing output buffers and a band-gap reference) consumes 37 mA from single 1.8 V voltage supply. For a 50 mV amplitude 60% modulation depth input AM signal it needs 100 s to stabilize the output. The frequency response of the circuit has almost a constant -3 dB bandwidth of 2.2 MHz. Its OIP3 result is at 19 dBm.

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“…[3]; a PGA circuit introduced in Ref. [4] has a dynamic gain range of 3-66 dB with 1 dB gain steps with a total of 64 steps. In Ref.…”

Section: Introductionmentioning

confidence: 99%

A differential automatic gain control circuit with two-stage −10 to 50 dB tuning range VGAs

Wang

Mao

Xiao³

et al. 2013

J. Semicond.

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A binary-weighted 64-dB programmable gain amplifier with a DCOC and AB-class buffer

et al. 2012

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This paper designs a binary-weighted programmable gain amplifier (PGA) with a DC offset cancellation (DCOC) circuit and an AB-class output buffer. The PGA adopts the circuit topology of a differential amplifier with diode-connected loads. Simulation shows that the performance of the PGA is not sensitive to temperature and process variation. According to test results, controlled by a digital signal of six bits, the PGA can realize a dynamic gain of -2 to 61 dB, and a gain step of 1 dB with a step error within ˙0.38 dB. The minimum 3 dB bandwidth is 92 MHz. At low-gain mode, IIP3 is 17 dBm, and a 1 dB compression point can reach 5.7 dBm. The DCOC circuit enables the amplifier to be used in a direct-conversion receiver and the AB-class output buffer circuit reduces the overall static power consumption.

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A programmable gain amplifier with a DC offset calibration loop for a direct-conversion WLAN transceiver

Cited by 2 publications

References 5 publications

A differential automatic gain control circuit with two-stage −10 to 50 dB tuning range VGAs

A differential automatic gain control circuit with two-stage −10 to 50 dB tuning range VGAs

A binary-weighted 64-dB programmable gain amplifier with a DCOC and AB-class buffer

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