A programmable method for low-power scan shift in SoC integrated circuits

Wang, Ran; Bhaskaran, Bonita; Natarajan, K.; Abdollahian, Ayub; Narayanun, Kaushik; Chakrabarty, Krishnendu; Sanghani, Amit

doi:10.1109/vts.2016.7477289

Cited by 19 publications

(2 citation statements)

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“…In addition, the added mux and clock gate increases the insertion delay on the functional clock. These overheads take a lot of design effort and add area due to clock buffering to balance Wang et al [28] presented a method to assign blocks to be used with a clock staggering technique. It considers the physical location and power supply network while assigning the blocks.…”

Section: Segmentation and Using Non-overlapping Or Staggered Clocksmentioning

confidence: 99%

Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

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While power reduction during testing is necessary for today's low-power devices, it also lowers test costs. Scan-based methods are the most widely used approach for testing integrated circuits (IC). Test vectors are shifted into and out of scan chains bit by bit during shift operation. The time required for shift operation dominates the test time. With the geometries shrinking (7 nm→5 nm→3 nm→1.8 nm), ICs are required to be tested for newer defects, increasing test time. The most effective way to reduce test time for scan operation is to increase the frequency of the shift operation. Reduction in shift power enables scan operation to be performed with increased frequency, reducing test time, and test cost. This paper presents a survey of techniques proposed recently for shift power reduction. Various techniques, including special flip-flop usage, segmentation, reordering, and low-pass filter, are being reviewed. The techniques are organized based on main attributes to underscore their similarities and differences. Pros and cons in terms of complexities involved in their implementation are discussed. We believe this paper will provide a point of reference for further studies in scan shift power reduction and will be helpful to both industry and academia.

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Section: Segmentation and Using Non-overlapping Or Staggered Clocksmentioning

confidence: 99%

Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

View full text Add to dashboard Cite

show abstract

“…Chapter 2-7 present results obtained in the course of the thesis research. These results have been published in [33][34][35][36][37][38][39][40][41][42]. Chapter 8 summarizes the contributions of the dissertation and describes directions for future research.…”

Section: Outline Of Dissertationmentioning

confidence: 99%