A Programmable SIMD Vision Chip for Real-Time Vision Applications

Wang, Miao; Lin, Qingyu; Zhang, Wancheng; Wu, Nanjian

doi:10.1109/jssc.2008.923621

Cited by 78 publications

(32 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It consists of an array of cells-that we also refer to as Processing Elements (PEs),-each comprising an Arithmetic Logic Unit (ALU) with some memory (registers) and including a photosensitive element to capture light. The architecture we consider also provides a way to communicate data from adjacent cells and is referred to as a Cellular Processor Array (CPA) [17,9,10]. Such a vision-chip architecture presents several advantages: first, by collocating a sensor with a processor array one benefits from very low latencies to access information.…”

Section: Hardware Implementation Of a Dnf Architecture For Tracking Cmentioning

confidence: 99%

A Neuromorphic Approach for Tracking using Dynamic Neural Fields on a Programmable Vision-chip

Martel

Sandamirskaya

2016

Proceedings of the 10th International Conference on Distributed Smart Camera

View full text Add to dashboard Cite

In artificial vision applications, such as tracking, a large amount of data captured by sensors is transferred to processors to extract information relevant for the task at hand. Smart vision sensors offer a means to reduce the computational burden of visual processing pipelines by placing more processing capabilities next to the sensor. In this work, we use a vision-chip in which a small processor with memory is located next to each photosensitive element. The architecture of this device is optimized to perform local operations. To perform a task like tracking, we implement a neuromorphic approach using a Dynamic Neural Field, which allows to segregate, memorize, and track objects. Our system, consisting of the vision-chip running the DNF, outputs only the activity that corresponds to the tracked objects. These outputs reduce the bandwidth needed to transfer information as well as further post-processing, since computation happens at the pixel level. ABSTRACTIn artificial vision applications, such as tracking, a large amount of data captured by sensors is transferred to processors to extract information relevant for the task at hand. Smart vision sensors offer a means to reduce the computational burden of visual processing pipelines by placing more processing capabilities next to the sensor. In this work, we use a vision-chip in which a small processor with memory is located next to each photosensitive element. The architecture of this device is optimized to perform local operations.To perform a task like tracking, we implement a neuromorphic approach using a Dynamic Neural Field, which allows to segregate, memorize, and track objects. Our system, consisting of the vision-chip running the DNF, outputs only the activity that corresponds to the tracked objects. These outputs reduce the bandwidth needed to transfer information as well as further post-processing, since computation happens at the pixel level.

show abstract

Section: Hardware Implementation Of a Dnf Architecture For Tracking Cmentioning

confidence: 99%

A Neuromorphic Approach for Tracking using Dynamic Neural Fields on a Programmable Vision-chip

Martel

Sandamirskaya

2016

Proceedings of the 10th International Conference on Distributed Smart Camera

View full text Add to dashboard Cite

show abstract

“…Compared to the conventional vision system with separate sensing and processing components, vision chips benefit from high performance computing without I/O bottleneck as well as small silicon area and reduced power consumption [1], [2], so these devices show good prospects in high speed image processing applications such as industrial machine vision, target tracking, and real-time surveillance. Programmable single instruction multiple data (SIMD) processors designed for vision chips show high speed performance in mid-level and low-level image processing [3].…”

Section: Introductionmentioning

confidence: 99%

A novel architecture of local memory for programmable SIMD vision chip

Chen

Yang

Cong

et al. 2013

2013 IEEE 10th International Conference on ASIC

View full text Add to dashboard Cite

This paper presents a novel architecture of the local memory for the programmable SIMD vision chip. The memory architecture consists of 8 × 8 local memory cells, among which each 8 static latches in the master stage share one dynamic latch in the slave stage. The local memory performs single bit read and write in each clock cycle, and the compact area of 14.33 m 2 /bit increases the integration level of the processor. A prototype chip with 64 × 64 processing units has been manufactured in 0.18 m CMOS technology. Five types of local memory architecture have been designed, and an 8-bit input data buffer based on dedicated latch structures has been designed as the input data buffer for each processing unit. Test results show that the presented structure is suitable for real-time computer vision applications such as the edge detection at the speed of 1000 fps.

show abstract

“…Application-specific vision chips in CMOS have been designed and demonstrated in analogue, digital, and mixed-signal technology. Miao et al also built a programmable ASIC with pixel-parallel processor elements for low-level operations and line-parallel processors for high-level operations [14]. They, therefore, used the parallel processor Xetal for low-level image processing and the serial digital signal processor TriMedia for high-level recognition tasks.…”

Section: Introductionmentioning

confidence: 99%

Realizing real‐time centroid detection of multiple objects with marching pixels algorithms on programmable customizing hardware

Fey

Reichenbach

Komann

et al. 2011

Concurrency and Computation

View full text Add to dashboard Cite

In this paper, we present a class of emergent algorithms called Marching Pixels and a corresponding programmable parallel chip architecture. Marching Pixels can be used for real-time image processing in smart camera chips. They are based on hardware agents, which are virtually crawling in a pixel grid image to find attributes like centroid, rotation, and size of an arbitrary number of objects given in an image. Because of the distributed and local processing scheme of Marching Pixels, reply times in milliseconds can be fulfilled. This means that time is determined where pre-known objects are located and how they are oriented to the main axes of the image. We present an example Marching Pixels algorithm and corresponding applicationspecific and programmable parallel architectures. The latter contains a specific instruction set that allows not only the execution of Marching Pixels algorithms but also of arbitrary Cellular Automata algorithms as an embedded parallel processor. The strengths and weaknesses of this architecture concerning the realization as field-programmable gate arrays and application-specific integrated circuits are discussed by means of hardware synthesis results. These results are compared with the solution achievable on a real hardware like the Atom processor. the camera in a way that work can be done in the requested time. The problem is, if image processing is serially performed using classic algorithms, it will be too slow even on fast single processors. For clarification, an example is given now. Let the image have classic VGA resolution of 640 480 pixels. This means a serial processor has to compute 307.200 pixels within the required reply time of 10 ms. Hence, only 32.6 ns remain for the computation of each pixel. To carry out a reasonable number of operations within this time range would require a clock cycle time of several GHz that one would like to avoid in embedded systems because of the high energy dissipation at such high frequencies.Our answer in order to both meet the strict real-time requirements and to be scalable with regard to increasing pixel resolutions are appropriate parallel low-level, that is hardware-oriented, algorithms, which are based mainly on local operators. These algorithms must not only work in parallel to be fast but also in a distributed way to be robust as well.The scalability in our algorithms is fulfilled by a kind of autonomous agents, which are instructed with the task to travel virtually within a pixel grid, which corresponds to the image, in order to find the centroids coordinates of objects given in this image. After the agents have found them, the corresponding coordinates are given to a robot control to enable the robot to grap the objects. Because these agents march around the pixels, they were given the name Marching Pixels (MPs). They have the goal to visit certain pixels and to gather data about the objects to which the pixels belong. The MP swarm shall further compress the gathered data in order to retrieve desired object information like size, ...

show abstract

A Programmable SIMD Vision Chip for Real-Time Vision Applications

Cited by 78 publications

References 14 publications

A Neuromorphic Approach for Tracking using Dynamic Neural Fields on a Programmable Vision-chip

A Neuromorphic Approach for Tracking using Dynamic Neural Fields on a Programmable Vision-chip

A novel architecture of local memory for programmable SIMD vision chip

Realizing real‐time centroid detection of multiple objects with marching pixels algorithms on programmable customizing hardware

Contact Info

Product

Resources

About