A Promising Planar Transistor with in-situ Doped Selective Si Epitaxy Technology (GORES MOSFET) for 32nm node and beyond

Abstract

node andbeyond. We demonstrated 40nm gate length "Gate Overlapped Raised Extension B, GORESMOSFET characteristic Structure: GORES MOSFET" without halo implantation and proofed that Id-Vg and Id-Vd characteristics of GORES are shown in Fig.6. Fig.7 shows the ultra shallow junction (USJ) could coexist with the reducing parasitic Roll off characteristics without halo implantation and about 40nm gate length resistance in GORES MOSFET. It is the new concept planar transistor with GORES MOSFET is demonstrated. In addition, we measured gate dielectric the gate overlapping the in-situ doped epitaxial extension to breakthrough the capacitance because of the GORES' unique gate dielectric shape, and the trade off relation between reducing parasitic resistance and suppression of the Tinvwere 2.11/2.16nm (nMOSFET/pMOSFET).We analyzed the advantage short channel effect (SCE) [1]. As a matter of course, it has the USJ and the of GORES MOSFET with the attention to both SCE and parasitic resistance low parasitic resistance (LPR) for 32nm node with in-situ doped selective Si by comparison with a conventional extension transistor. We discussed the Epitaxy (ISDSE). effect ofthe ultra shallowjunction and the scalability ofparasitic resistance of Introduction GORES MOSFETs.Drain Induce Barrier Lowering (DIBL) is one of the Recently it has been difficult to improve the transistor performance due to