A PVT variation-tolerant static single-phase clocked dual-edge triggered flip-flop for aggressive voltage scaling

Lee, Yongmin

doi:10.1587/elex.16.20190528

Cited by 3 publications

(3 citation statements)

References 31 publications

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“…(%) DETFF TP t cq PDP LM1 [13] 36.18 31.68 16.19 LM2 [13] 2267.70 24.34 94.16 TCRFF [16] 26.48 39.59 55.71 LM C [15] 10.03 32.26 38.00 LG C [19] 21.99 41.80 54.72 IP C [19] 19.22 37.01 49.25 FN C [19] 4.68 34.15 37.41 EP1 [21] 51.05 4.88 53.56 EP2 [22] 66.58 5.36 64.89 SSPC [25] 7 3, the flip-flop proposed in this paper is superior to all the comparative DETFFs in terms of the total circuit power consumption, saving an average of 251.17% of the total power consumption. Moreover, it improved the average PDP by 44.32% and the delay by 9.71%.…”

Section: Experimental Results and Comparative Analysismentioning

confidence: 99%

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Anti-interference low-power double-edge triggered flip-flop based on C-elements

Huang

Yang

Song

et al. 2022

Tsinghua Sci. Technol.

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When the input signal has been interfered and glitches occur, the power consumption of Double-Edge Triggered Flip-Flops (DETFFs) will significantly increase. To effectively reduce the power consumption, this paper presents an anti-interference low-power DETFF based on C-elements. The improved C-element is used in this DETFF, which effectively blocks the glitches in the input signal, prevents redundant transitions inside the DETFF, and reduces the charge and discharge frequencies of the transistor. The C-element has also added pull-up and pull-down paths, reducing its latency. Compared with other existing DETFFs, the DETFF proposed in this paper only flips once on the clock edge, which greatly reduces the redundant transitions caused by glitches and effectively reduces power consumption. This paper uses HSPICE to simulate the proposed DETFF and other 10 DETFFs.The findings show that compared with the other 10 types of DETFFs, the proposed DETFF has achieved large performance indexes in the total power consumption, total power consumption with glitches, delays, and power delay product. A detailed analysis of variance indicates that the proposed DETFF features less sensitivity to process, voltage, temperature, and Negative Bias Temperature Instability (NBTI)-induced aging variations.

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Section: Experimental Results and Comparative Analysismentioning

confidence: 99%

“…(%) DETFF G2 G4 LM1 [13] 48.71 58.02 LM2 [13] 94.72 94.73 TCRFF [16] 45.86 58.41 LM C [15] 28.23 43.05 LG C [19] 38.45 48.95 IP C [19] 17.95 19.57 FN C [19] 16.46 26.65 EP1 [21] 49.23 50.65 EP2 [22] 65.87 66.42 SSPC [25] 30.71 46.38 Average 43.62 51.28…”

Section: Variance Analysismentioning

confidence: 99%

Anti-interference low-power double-edge triggered flip-flop based on C-elements

Huang

Yang

Song

et al. 2022

Tsinghua Sci. Technol.

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“…Flip-flops occupy a large portion of chip area and contribute a significant part of overall power in the system. It has been reported that flip-flops and last sections of clock distribution network that directly drive flip-flops account for 90% of the clock system power [14,15,16]. It is crucial to design low-power radiation-hardened flip-flops with low penalties to meet strict demands of the industry.…”

Section: Introductionmentioning

confidence: 99%

A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design

Jin

Zhang

et al. 2021

IEICE Electron. Express

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A power-efficient Single Event Upset (SEU) -tolerant pulsetriggered flip-flop design is presented. The dual-modular redundant design takes advantage of concise formation of pulse-triggered designs, and avoids the disadvantages of it, such as high power consumption. Clock-gating scheme is applied to reduce power consumption. The static configuration and the avoidance of contention mechanism led to the balance of power consumption, speed and SEU tolerance. The SEU tolerance is evaluated by means of SEU cross section, which is significantly lower than conventional D flip-flop. The proposed flip-flop is designed in 55nm CMOS technology to evaluate performances. The proposed design achieves the lowest power consumption, which is even lower than conventional D flip-flop. Although the speed is sacrificed, the lowest power-delay product is achieved among hardened designs. The proposed design provides solution to speedinsensitive and power-constrained applications.

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Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements

Huang

Zhong

Duan

et al. 2022

J CIRCUIT SYST COMP

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Glitch at the input can increase the power consumption of flip-flop greatly. To solve this problem effectively, a Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements (LARC) is proposed in this paper. The proposed Latch Multiplexer-A Double-edge Triggered Flip-flop (LARC-DET) can effectively block the glitch at the input and prevent the redundant transition at internal nodes. As a result, the extra power consumption caused by the glitch at the input is effectively reduced. The simulation was performed using HSPICE under 32[Formula: see text]nm complementary metal oxide semiconductor (CMOS) process. The simulation results show that, compared with 12 double edge flip-flops, the proposed LARC-DET is the lowest in terms of power consumption and power delay product. Process voltage temperature (PVT) variation analysis shows its insensitivity to voltage variation, temperature variation and process variation.

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A PVT variation-tolerant static single-phase clocked dual-edge triggered flip-flop for aggressive voltage scaling

Cited by 3 publications

References 31 publications

Anti-interference low-power double-edge triggered flip-flop based on C-elements

Anti-interference low-power double-edge triggered flip-flop based on C-elements

A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design

Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements

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