A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator

Chae, Joo-Hyung; Ko, Hyeongjun; Park, Jihwan; Kim, Suhwan

doi:10.1109/tvlsi.2018.2883730

Cited by 18 publications

(10 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Generally speaking, analog architectures of DCC [7][8][9][10][11] usually take a feedback form, which can have higher resolution and operating frequency, but with a lengthy lock time. Digital architectures are usually a non-feedback type [10][11][12][13][14][15][16][17][18][19][20][21][22], and thus have a faster lock time. The high degree of circuit integration and the easy design of Digital architectures make the realization of this circuit more advantageous and developmental than the analog architectures.…”

Section: State-of-the-artmentioning

confidence: 99%

“…The digital-falling edge modulator modulates each falling edge of input clock and inverted input clock, and stretches or shrinks by as much as half of the edge difference. Afterwards, the phase interpolator is performed and to interpolate the two modulated clock, the final output clock generated with 50% duty cycle in [22] has benefits with respect to covering a wide frequency range and fast locking time in 5 cycles. The relaxation oscillator is designed in [22] to detect duty-cycle and quadrature phase errors by converting them into two frequencies.…”

Section: State-of-the-artmentioning

confidence: 99%

See 1 more Smart Citation

A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock

Kao

2021

Electronics

View full text Add to dashboard Cite

This paper proposes an all-digital duty cycle corrector with synchronous fast locking, and adopts a new quantization method to effectively produce a phase of 180 degrees or half delay of the input clock. By taking two adjacent rising edges input to two delay lines, the total delay time of the delay line is twice the other delay line. This circuit uses a 0.18 μm CMOS process, and the overall chip area is 0.0613 mm2, while the input clock frequency is 500 MHz to 1000 MHz, and the acceptable input clock duty cycle range is 20% to 80%. Measurement results show that the output clock duty cycle is 50% ± 2.5% at a supply voltage of 1.8 V operating at 1000 MHz, the power consumed is 10.1 mW, with peak-to-peak jitter of 9.89 ps.

show abstract

Section: State-of-the-artmentioning

confidence: 99%

Section: State-of-the-artmentioning

confidence: 99%

A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock

Kao

2021

Electronics

View full text Add to dashboard Cite

show abstract

“…With this trend, increasing data-rate and clock frequency is required but this is limited by low-performance DRAM process [3]. Quarter-rate design has been implemented in recent memory interfaces to increase data-rate while achieving a more relaxed timing margin and lower power consumption than half-rate design [4,5].…”

Section: Introductionmentioning

confidence: 99%

“…For quarter-rate operation in the memory interface, quadrature clocks are generated by dividing high-speed differential clocks [4][5][6]. Skew between the quadrature clocks at the destination is introduced due to noise, mismatch and process, voltage, and temperature (PVT) variation of the clock distribution.…”

Section: Introductionmentioning

confidence: 99%

A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces

Park

Lee

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

Self Cite

View full text Add to dashboard Cite

In this paper, a quadrature signal corrector (QSC) with high accuracy and fast correction for memory interfaces is presented. An adaptive delay gain controller in the QSC adjusts each delay gain of four digitally controlled delay lines (DCDLs) separately depending on skew between the quadrature clocks, resulting in short correction time together with low residual skew. To validate the effectiveness of our QSC in memory interfaces, a quarter-rate single-ended 1-tap decision feedback equalizer (DFE) with the QSC was fabricated in a 65nm CMOS process. Using the adaptive delay gain controller, the QSC reduced the skew between the 3 GHz quadrature clocks from a maximum of 21.2 ps to 0.8 ps while correction time was reduced by a factor of 3.9 compared to that without using the adaptive delay gain controller. At 12 Gb/s, the DFE using our QSC achieved a BER of 10 −12 with an eye width of 140 mUI when the input clock skew is 13.2 ps.

show abstract

“…To eliminate the clock duty-cycle errors in memory interface channels, input clock buffers, and on-chip clock trees, typical high-speed DRAM and memory controllers utilize analog-type, digital-type or hybrid-type duty-cycle corrector (DCC) circuits [1,2,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20]. The DCCs in DDR3, DDR4, LPDDR4, LPDDR5, and GDDR5 SDRAM applications performs duty-cycle error compensation of high-speed signal pins for a differential clock (CK/CKb), data signals (DQs), and a data strobe signal (DQS).…”

Section: Introductionmentioning

confidence: 99%

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

Hwang

Kim

2019

IEICE Electron. Express

View full text Add to dashboard Cite

This Letter presents a 0.8-3.4 GHz process variation insensitive full-swing duty-cycle corrector (DCC) for high-speed memory I/O links. The proposed DCC utilizes a new full-swing duty cycle adjuster (DCA) that can provide a full-swing output clock of 50% duty-cycle without using a small-swing to full-swing level shifter. The proposed full-swing DCA is based on a new pseudo-differential feedback delay element (PFDE) and fundamentally eliminates the problem of increased duty-cycle errors due to the use of a level shifter that is vulnerable to process corner variation. The proposed DCC is implemented in a 40-nm CMOS process and achieves an operating frequency range of 0.8-3.4 GHz. The duty-cycle correction range is ²15% at 3.4 GHz. The DCC dissipates 2.8 mW from a 1.0 V supply at 3.4 GHz and occupies an active area of only 0.0054 mm 2 .

show abstract

A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator

Cited by 18 publications

References 17 publications

A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock

A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock

A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

Contact Info

Product

Resources

About