A quantitative analysis on microarchitectures of modern CPU-FPGA platforms

Choi, Y.; Cong, Jason; Fang, Zhenman; Yan, Hao; Reinman, Glenn; Wei, Peng

doi:10.1145/2897937.2897972

Cited by 106 publications

(46 citation statements)

References 13 publications

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“…FPGAs are reprogrammable off-theshelf circuits and are ideal for general-purpose hardware acceleration. Typically, high-performance cloud solutions use high-end FPGA tightly coupled with general-purpose multicore processors [26], while ASIC is used for more throughput or in battery-powered embedded devices.…”

Section: Purpose-built Hardware For Tnnmentioning

confidence: 99%

Ternary neural networks for resource-efficient AI applications

Alemdar

Leroy

Prost-Boucle

et al. 2017

2017 International Joint Conference on Neural Networks (IJCNN)

176

118

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The computation and storage requirements for Deep Neural Networks (DNNs) are usually high. This issue limits their deployability on ubiquitous computing devices such as smart phones, wearables and autonomous drones. In this paper, we propose ternary neural networks (TNNs) in order to make deep learning more resource-efficient. We train these TNNs using a teacher-student approach based on a novel, layer-wise greedy methodology. Thanks to our two-stage training procedure, the teacher network is still able to use state-of-the-art methods such as dropout and batch normalization to increase accuracy and reduce training time. Using only ternary weights and activations, the student ternary network learns to mimic the behavior of its teacher network without using any multiplication. Unlike its {-1,1} binary counterparts, a ternary neural network inherently prunes the smaller weights by setting them to zero during training. This makes them sparser and thus more energy-efficient. We design a purpose-built hardware architecture for TNNs and implement it on FPGA and ASIC. We evaluate TNNs on several benchmark datasets and demonstrate up to 3.1× better energy efficiency with respect to the state of the art while also improving accuracy.

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Section: Purpose-built Hardware For Tnnmentioning

confidence: 99%

Ternary neural networks for resource-efficient AI applications

Alemdar

Leroy

Prost-Boucle

et al. 2017

2017 International Joint Conference on Neural Networks (IJCNN)

176

118

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“…The third point deals with accelerator design reuse and portability. The accelerator GRN generator presented in the work of da Silva et al has a memory interface customized to get the maximum performance for the first Intel CPU‐FPGA platform, which was discontinued. Therefore, we create an accelerator unit by reusing the GRN kernel from the aforementioned work as shown a simplified diagram in Figure C.…”

Section: Performance Metrics and Analysismentioning

confidence: 99%

“…In our previous work ADD Harp1, 12 the target platform was the first Intel CPU/FPGA prototype where an accelerator hardware module (AHM) occupies the other processor socket in a 2-socket motherboard, 33 and the peak bandwidth between the CPU memory and FPGA is 7 GB/sec for read and 5 GB/sec for write operations. 33 The software API was based on the Intel Accelerator abstraction layer SDK, which differs from our current work based on Intel OPAE SDK, 13 since this first prototype was discontinued. As an initial proof of concept, six showcasing examples for this first Intel prototype platform have been compared to a CPU implementation in our previous work.…”

Section: Signal Processing and Map-and-reduce Benchmarksmentioning

confidence: 99%

ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing

Penha

Silva

et al. 2018

Concurrency and Computation

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Summary Dataflow‐based FPGA accelerators have become a promising alternative to deliver energy‐efficient high‐performance computing. However, FPGA programming is still a challenge. This paper presents Accelerator Design and Deploy (ADD), a high‐level framework to specify, to simulate, and to implement dataflow accelerators for streaming applications. The framework includes an open dataflow operator library, and templates are provided to easily design new operators. The framework also provides a high‐level and an accurate simulation at circuit level with short execution times. Moreover, ADD provides software and hardware APIs to simplify the integration process, extending the benefits of portability from low‐cost FPGA boards to high performance datacenter FPGA platforms. Our framework supports coupling with high‐level programming languages, and it has been validated on two FPGA platforms: the Intel high‐performance CPU‐FPGA heterogeneous computing platform and an educational FPGA kit. We show that our simple approach presents competitive performance, both in time and energy, when compared to multi‐core and GPU accelerators.

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“…Field Programmable Gate Arrays (FPGAs) are seen as an attractive proposition to address energy issues and are used in the IvyTown Xeon + Stratix V FPGA system [6] and Amazon's Elastic Compute Cloud (EC2) F1 instances. Issues include the need for specialist programming languages and the lengthy synthesis times.…”

Section: Introductionmentioning

confidence: 99%

NanoStreams: A Microserver Architecture for Real-Time Analytics on Fast Data Streams

Minhas

Russell

Kaloutsakis

et al. 2018

IEEE Trans. Multi-Scale Comp. Syst.

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Abstract-Ever increasing power consumption has created great interest in energy-efficient microserver architectures but they lack the computational, networking and storage power necessary to cope with real-time data analytics. We propose NanoStreams, an integrated architecture comprising an ARM-based microserver, coupled via a novel, low latency network interface, Nanowire, to a Analytics-on-Chip architecture implemented on Field Programmable Gate Array (FPGA) technology; the architecture comprises ARM cores for performing low latency transactional processing, integrated with programmable, energy efficient Nanocore processors for high-throughput streaming analytics. The paper outlines the complete system architecture, hardware level detail, compiler, network protocol, and programming environment. We present experiments with an industrial workload from the financial services sector, comparing a state-of-the-art server based on Intel Sandy Bridge processors, an ARM based Calxeda ECS-1000 microserver and ODROID XU3 node, with the NanoStreams microserver architecture. For end-to-end workload, the NanoStreams microserver achieves energy savings up to 10.7×, 5.87× and 5× compared to the Intel server, Calxeda microserver and ODROID node respectively.

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A quantitative analysis on microarchitectures of modern CPU-FPGA platforms

Cited by 106 publications

References 13 publications

Ternary neural networks for resource-efficient AI applications

Ternary neural networks for resource-efficient AI applications

ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing

NanoStreams: A Microserver Architecture for Real-Time Analytics on Fast Data Streams

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