A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

Hansson, Andreas; Goossens, Kees

doi:10.1007/s10617-011-9073-7

Cited by 8 publications

(4 citation statements)

References 67 publications

(145 reference statements)

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“…Performance for NoC can be measured in terms of average latency, throughput, power and energy of the network [26–30]. Different NoC networks need a different number of routers with varying degree of ports to link routers and nodes in the networks.…”

Section: Performance Vs Cost Comparisonmentioning

confidence: 99%

A New Cross-By-Pass-Torus Architecture Based on CBP-Mesh and Torus Interconnection for On-Chip Communication

et al. 2016

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A Mesh topology is one of the most promising architecture due to its regular and simple structure for on-chip communication. Performance of mesh topology degraded greatly by increasing the network size due to small bisection width and large network diameter. In order to overcome this limitation, many researchers presented modified Mesh design by adding some extra links to improve its performance in terms of network latency and power consumption. The Cross-By-Pass-Mesh was presented by us as an improved version of Mesh topology by intelligent addition of extra links. This paper presents an efficient topology named Cross-By-Pass-Torus for further increase in the performance of the Cross-By-Pass-Mesh topology. The proposed design merges the best features of the Cross-By-Pass-Mesh and Torus, to reduce the network diameter, minimize the average number of hops between nodes, increase the bisection width and to enhance the overall performance of the network. In this paper, the architectural design of the topology is presented and analyzed against similar kind of 2D topologies in terms of average latency, throughput and power consumption. In order to certify the actual behavior of proposed topology, the synthetic traffic trace and five different real embedded application workloads are applied to the proposed as well as other competitor network topologies. The simulation results indicate that Cross-By-Pass-Torus is an efficient candidate among its predecessor’s and competitor topologies due to its less average latency and increased throughput at a slight cost in network power and energy for on-chip communication.

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Section: Performance Vs Cost Comparisonmentioning

confidence: 99%

A New Cross-By-Pass-Torus Architecture Based on CBP-Mesh and Torus Interconnection for On-Chip Communication

et al. 2016

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“…[6] focuses on a multi-channel memory controller with 256-byte transactions that are interleaved over multiple channels. Since our memory controller has a single channel, we use smaller transaction sizes, which are also current practice in today's systems [7], [10]. CPU and IP have cache-lines of 64 bytes, while those of the GPU are 128 bytes.…”

Section: Variable Transaction Sizesmentioning

confidence: 99%

Modeling and Verification of Dynamic Command Scheduling for Real-Time Memory Controllers

Åkesson

Lampka

et al. 2016

2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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In modern multi-core systems with multiple realtime (RT) applications, memory traffic accessing the shared SDRAM is increasingly diverse, e.g., transactions have variable sizes. RT memory controllers with dynamic command scheduling can efficiently address the diversity by issuing appropriate commands subject to the SDRAM timing constraints. However, the scheduling dependencies between commands make it challenging to derive tight bounds for the worst-case response time (WCRT) and the worst-case bandwidth (WCBW) of a memory controller. Existing modeling and analysis techniques either do not provide tight WCRT and WCBW bounds for diverse memory traffic with variable transaction sizes or are difficult to adapt to different RT memory controllers. This paper models a memory controller using Timed Automata (TA), where model checking is applied for analysis. Our TA model is modular and accurately captures the behavior of a RT memory controller with dynamic command scheduling.We obtain WCRT and WCBW bounds, which are validated by simulating the worst-case transaction traces obtained by model checking with a cycle-accurate model of the memory controller. Our method outperforms three state-of-the-art analysis techniques. We reduce WCRT bound by up to 20%, while the average improvement is 7.7%, and increase the WCBW bound by up to 25% with an average improvement of 13.6%. In addition, our modeling is generic enough to extend to memory controllers with different mechanisms.

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“…However, these works do not show how NoC solution overall can be resourced efficiently for application specific demands. A state-of-the-art end to end design flow using manual or regular topology and guaranteeing resources can be found in [ 3 ].…”

Section: Related Workmentioning

confidence: 99%

Designing Area Optimized Application-Specific Network-On-Chip Architectures while Providing Hard QoS Guarantees

et al. 2015

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With the increase of transistors' density, popularity of System on Chip (SoC) has increased exponentially. As a communication module for SoC, Network on Chip (NoC) framework has been adapted as its backbone. In this paper, we propose a methodology for designing area-optimized application specific NoC while providing hard Quality of Service (QoS) guarantees for real time flows. The novelty of the proposed system lies in derivation of a Mixed Integer Linear Programming model which is then used to generate a resource optimal Network on Chip (NoC) topology and architecture while considering traffic and QoS requirements. We also present the micro-architectural design features used for enabling traffic and latency guarantees and discuss how the solution adapts for dynamic variations in the application traffic. The paper highlights the effectiveness of proposed method by generating resource efficient NoC solutions for both industrial and benchmark applications. The area-optimized results are generated in few seconds by proposed technique, without resorting to heuristics, even for an application with 48 traffic flows.

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A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

Cited by 8 publications

References 67 publications

A New Cross-By-Pass-Torus Architecture Based on CBP-Mesh and Torus Interconnection for On-Chip Communication

A New Cross-By-Pass-Torus Architecture Based on CBP-Mesh and Torus Interconnection for On-Chip Communication

Modeling and Verification of Dynamic Command Scheduling for Real-Time Memory Controllers

Designing Area Optimized Application-Specific Network-On-Chip Architectures while Providing Hard QoS Guarantees

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