A Quarter Pel Full Search Block Motion Estimation Architecture for H. 264/AVC

Rahman, C.A.; Badawy, W.

doi:10.1109/icme.2005.1521448

Cited by 18 publications

(11 citation statements)

References 5 publications

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“…Performance of the proposed architecture has been compared with other existing architectures [19,[22][23][24][25]. It is found that proposed architecture has several advantages over other existing architectures (see Table 2).…”

Section: Hardware Comparisonmentioning

confidence: 98%

“…To solve the memory bandwidth limitation, several techniques have been developed, e.g., (1) caching, (2) memory interleaving, (3) parallel memory banks, (4) pipelining, and (5) hierarchical memory [19]. In this paper, to efficiently reduce memory access conflicts and reuse data, a multiport memory network architecture is used, in which there are four banks to buffer the search window (SW) data, current block (CB) data and MVs.…”

Section: Memory Networkmentioning

confidence: 99%

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A robust motion estimation with center-biased diamond search and its parallel architecture for motion-compensated de-interlace

Ding

Yan

2010

J Supercomput

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For motion compensated de-interlace, the accuracy and reliability of the motion vectors have a significant impact on the performance of the motion compensated interpolation. In order to improve the robustness of motion vector, a novel motion estimation algorithm with center-biased diamond search and its parallel VLSI architecture are proposed in this paper. Experiments show that it works better than conventional motion estimation algorithms in terms of motion compensation error and robustness, and its architecture overcomes the irregular data flow and achieves high efficiency. It also efficiently reuses data and reduces the control overhead. So, it is highly suitable for HDTV applications.

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Section: Hardware Comparisonmentioning

confidence: 98%

Section: Memory Networkmentioning

confidence: 99%

A robust motion estimation with center-biased diamond search and its parallel architecture for motion-compensated de-interlace

Ding

Yan

2010

J Supercomput

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“…The architecture described in [21] reduces the search area and number of MVs needed in order to achieve low-latency and hardware efficiency. Finally, designs suitable for a FPGA implementation are presented in [22,23] In this paper, a VLSI architecture based on the full-search algorithm for implementation of FME is described. Its architecture is made up of three different pipeline processors: a half-pixel processor, a quarter-pixel processor and a mode decision processor.…”

Section: Introductionmentioning

confidence: 99%

An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV

Ruiz

Michell

2010

J Sign Process Syst

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Fractional Motion Estimation (FME) in highdefinition H.264 presents a significant design challenge in terms of memory bandwidth, latency and area cost as there are various modes and complex mode decision flow, which require over 45% of the computation complexity in the H.264 encoding process. In this paper, a new highperformance VLSI architecture for Fractional Motion Estimation (FME) in H.264/AVC based on the full-search algorithm is presented. This architecture is made up of three different pipeline processors to establish a trade-off between processing time and hardware utilization. The computing scheme based on a 4-pixel interpolation unit with a 10-pixel input bandwidth is capable of processing a macroblock (MB) in 870 clock cycles. The final VLSI implementation only requires 11.4 k gates and 4.4kBytes of RAM in a standard 180 nm CMOS technology operating at 290 MHz. Our design generates the residual image and the best MVs and mode in a high throughput and low area cost architecture while achieving enough processing capacity for 1080HD (1920×1088@30fps) real-time video streams.

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“…Although VBS-BMA achieves higher coding performance than that of FBS-BMA, it requires a high computation effort since 41 motion vectors of 7 different sizes should be computed for each macroblock. Therefore, many efficient hardware architectures such as systolic array [8], 1-D processing element (PE) array [6] and 2-D PE array [4] [7] [10] have been proposed for implementing VBS-BMA. The 1-D PE array is a simple structure, as it is easier to control and less gates than a 2-D PE array, but it is normal to search the sum of absolute difference (SAD) against only one row or a column of the macroblock at a time.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Hardware Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC

Pyen

Min

Chong

et al. 2006

Advances in Visual Computing

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Abstract. In this paper, we propose a high speed hardware architecture for the implementation of full-search variable block size motion estimation (VBSME) suitable for high quality video compression. In the high-quality video with large frame size and search range, the memory bandwidth is mainly responsible for throughput limitations and power consumption in VBSME. The proposed architecture is designed for reducing the memory bandwidth by adopting "meander"-like scan for a high overlapped data of the search area and using onchip memory to reuse the overlapped data. We can reuse the previous candidate block of 94% to the current one and save about 23% memory access cycles in a search range of [-16, +15]. The architecture has been prototyped in Verilog HDL, simulated by ModelSim and synthesized by Synopsys Design Compiler with Samsung 0.18um standard cell library. Under a clock frequency of 51MHz, The simulation result shows that the architecture can achieve the realtime processing of 720x576 picture size at 30fps with the search range of [-16~+15].

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A Quarter Pel Full Search Block Motion Estimation Architecture for H. 264/AVC

Cited by 18 publications

References 5 publications

A robust motion estimation with center-biased diamond search and its parallel architecture for motion-compensated de-interlace

A robust motion estimation with center-biased diamond search and its parallel architecture for motion-compensated de-interlace

An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV

An Efficient Hardware Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC

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