A real-time communication method for wormhole switching networks

Kim, Byungjae; Kim, Jong; Hong, SungJe; Lee, Sunggu

doi:10.1109/icpp.1998.708526

Cited by 10 publications

(8 citation statements)

References 9 publications

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“…Most of the real-time analytical models for priority-based wormhole NoCs have been based on analysis developed in the mid 1990s for general purpose wormhole networks [22] [11] [16]. NoC analysis models proposed by Shi and Burns [30] and Kashif and Patel [14] customised those general models for the specifics of the on-chip communication mechanisms and were widely used until the discovery of the multi-point progressive blocking (MPB) problem by Xiong et al [35].…”

Section: Background 21 Real-time Wormhole Network-on-chipmentioning

confidence: 99%

Real-Time Guarantees in Routerless Networks-on-Chip

Soares Indrusiak,

Burns

2023

ACM Trans. Embed. Comput. Syst.

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This paper considers the use of routerless networks-on-chip as an alternative on-chip interconnect for multiprocessor systems requiring hard real-time guarantees for inter-processor communication. It presents a novel analytical framework that can provide latency upper bounds to real-time packet flows sent over routerless networks-on-chip, and it uses that framework to evaluate the ability of such networks to provide real-time guarantees. Extensive comparative analysis is provided, considering different architectures for routerless networks and a state-of-the-art wormhole network based on priority-preemptive routers as a baseline.

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Section: Background 21 Real-time Wormhole Network-on-chipmentioning

confidence: 99%

Real-Time Guarantees in Routerless Networks-on-Chip

Soares Indrusiak,

Burns

2023

ACM Trans. Embed. Comput. Syst.

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“…In this paper we explore real-time communication in wormhole switching for on-chip networks. Utilizing the priority based preemption arbitration (Balakrishnan & Ozguner, 1998;Hary & Ozguner, 1997;Kim, Kim, Hong, & Lee, 1998;Lu, Jantsch, & Sander, 2005), a novel real-time schedulability analysis approach is presented which successfully emulate wormhole switching as classic single processor scheduling model (Liu & Layland, 1973). By evaluating diverse inter-relationships and service attributes among the traffic-flows, this approach can predict the packet transmission latency for a given traffic-flow based on three quantifiable different interferences: direct interference from higher priority traffic-flows, indirect interference from higher priority traffic-flows and self-blocking produced by the previous packet from same traffic-flow.…”

mentioning

confidence: 99%

Schedulability Analysis for Real Time On-Chip Communication with Wormhole Switching

Burns

Indrusiak

Shi

2010

International Journal of Embedded and Real-Time Communication Systems

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In this paper, the authors discuss a real-time on-chip communication service with a priority-based wormhole switching policy. The authors present a novel off-line schedulability analysis approach, worst case network latency analysis. By evaluating diverse inter-relationships and service attributes among the traffic flows, this approach can predict the packet network latency for all practical situations. The simulation results provide evidence that communication latency calculated using the real time analysis approach is safe, closely matching the figures obtained from simulation.

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“…Similarly, when computing the contention delay for a packet, we assume that, by the time it is injected in the network, any other potential contending flow is also active at that moment, transmitting its packets in a way that it produces the worst-case contention scenario. In order to reproduce the worst-case contention scenario we need to consider the worst direct contention and the worst indirect contention [84]. The former can be easily reproduced by considering that for a packet r k i of F i at every hop, all possible contenders (i.e.…”

Section: Fixed Parametersmentioning

confidence: 99%

“…Additionally, requests not sharing the path with r 1 i can be blocking r k j which in turns causes contention in r 1 1 . This contention is usually regarded as indirect contention [84].…”

Section: Worst Contentionmentioning

confidence: 99%

A time-predictable many-core processor design for critical real-time embedded systems

Panić

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Critical Real-Time Embedded Systems (CRTES) are in charge of controlling fundamental parts of embedded system, e.g. energy harvesting solar panels in satellites, steering and breaking in cars, or flight management systems in airplanes. To do so, CRTES require strong evidence of correct functional and timing behavior. The former guarantees that the system operates correctly in response of its inputs; the latter ensures that its operations are performed within a predefined time budget. CRTES aim at increasing the number and complexity of functions. Examples include the incorporation of \smarter" Advanced Driver Assistance System (ADAS) functionality in modern cars or advanced collision avoidance systems in Unmanned Aerial Vehicles (UAVs). All these new features, implemented in software, lead to an exponential growth in both performance requirements and software development complexity. Furthermore, there is a strong need to integrate multiple functions into the same computing platform to reduce the number of processing units, mass and space requirements, etc. Overall, there is a clear need to increase the computing power of current CRTES in order to support new sophisticated and complex functionality, and integrate multiple systems into a single platform. The use of multi- and many-core processor architectures is increasingly seen in the CRTES industry as the solution to cope with the performance demand and cost constraints of future CRTES. Many-cores supply higher performance by exploiting the parallelism of applications while providing a better performance per watt as cores are maintained simpler with respect to complex single-core processors. Moreover, the parallelization capabilities allow scheduling multiple functions into the same processor, maximizing the hardware utilization. However, the use of multi- and many-cores in CRTES also brings a number of challenges related to provide evidence about the correct operation of the system, especially in the timing domain. Hence, despite the advantages of many-cores and the fact that they are nowadays a reality in the embedded domain (e.g. Kalray MPPA, Freescale NXP P4080, TI Keystone II), their use in CRTES still requires finding efficient ways of providing reliable evidence about the correct operation of the system. This thesis investigates the use of many-core processors in CRTES as a means to satisfy performance demands of future complex applications while providing the necessary timing guarantees. To do so, this thesis contributes to advance the state-of-the-art towards the exploitation of parallel capabilities of many-cores in CRTES contributing in two different computing domains. From the hardware domain, this thesis proposes new many-core designs that enable deriving reliable and tight timing guarantees. From the software domain, we present efficient scheduling and timing analysis techniques to exploit the parallelization capabilities of many-core architectures and to derive tight and trustworthy Worst-Case Execution Time (WCET) estimates of CRTES. Los sistemas críticos empotrados de tiempo real (en ingles Critical Real-Time Embedded Systems, CRTES) se encargan de controlar partes fundamentales de los sistemas integrados, e.g. obtención de la energía de los paneles solares en satélites, la dirección y frenado en automóviles, o el control de vuelo en aviones. Para hacerlo, CRTES requieren fuerte evidencias del correcto comportamiento funcional y temporal. El primero garantiza que el sistema funciona correctamente en respuesta de sus entradas; el último asegura que sus operaciones se realizan dentro de unos limites temporales establecidos previamente. El objetivo de los CRTES es aumentar el número y la complejidad de las funciones. Algunos ejemplos incluyen los sistemas inteligentes de asistencia a la conducción en automóviles modernos o los sistemas avanzados de prevención de colisiones en vehiculos aereos no tripulados. Todas estas nuevas características, implementadas en software,conducen a un crecimiento exponencial tanto en los requerimientos de rendimiento como en la complejidad de desarrollo de software. Además, existe una gran necesidad de integrar múltiples funciones en una sóla plataforma para así reducir el número de unidades de procesamiento, cumplir con requisitos de peso y espacio, etc. En general, hay una clara necesidad de aumentar la potencia de cómputo de los actuales CRTES para soportar nueva funcionalidades sofisticadas y complejas e integrar múltiples sistemas en una sola plataforma. El uso de arquitecturas multi- y many-core se ve cada vez más en la industria CRTES como la solución para hacer frente a la demanda de mayor rendimiento y las limitaciones de costes de los futuros CRTES. Las arquitecturas many-core proporcionan un mayor rendimiento explotando el paralelismo de aplicaciones al tiempo que proporciona un mejor rendimiento por vatio ya que los cores se mantienen más simples con respecto a complejos procesadores de un solo core. Además, las capacidades de paralelización permiten programar múltiples funciones en el mismo procesador, maximizando la utilización del hardware. Sin embargo, el uso de multi- y many-core en CRTES también acarrea ciertos desafíos relacionados con la aportación de evidencias sobre el correcto funcionamiento del sistema, especialmente en el ámbito temporal. Por eso, a pesar de las ventajas de los procesadores many-core y del hecho de que éstos son una realidad en los sitemas integrados (por ejemplo Kalray MPPA, Freescale NXP P4080, TI Keystone II), su uso en CRTES aún precisa de la búsqueda de métodos eficientes para proveer evidencias fiables sobre el correcto funcionamiento del sistema. Esta tesis ahonda en el uso de procesadores many-core en CRTES como un medio para satisfacer los requisitos de rendimiento de aplicaciones complejas mientras proveen las garantías de tiempo necesarias. Para ello, esta tesis contribuye en el avance del estado del arte hacia la explotación de many-cores en CRTES en dos ámbitos de la computación. En el ámbito del hardware, esta tesis propone nuevos diseños many-core que posibilitan garantías de tiempo fiables y precisas. En el ámbito del software, la tesis presenta técnicas eficientes para la planificación de tareas y el análisis de tiempo para aprovechar las capacidades de paralelización en arquitecturas many-core, y también para derivar estimaciones de peor tiempo de ejecución (Worst-Case Execution Time, WCET) fiables y precisas.

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A real-time communication method for wormhole switching networks

Cited by 10 publications

References 9 publications

Real-Time Guarantees in Routerless Networks-on-Chip

Real-Time Guarantees in Routerless Networks-on-Chip

Schedulability Analysis for Real Time On-Chip Communication with Wormhole Switching

A time-predictable many-core processor design for critical real-time embedded systems

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