2011 IEEE International Conference on Consumer Electronics -Berlin (ICCE-Berlin) 2011
DOI: 10.1109/icce-berlin.2011.6031866
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A real-time Ethernet prototype platform for automotive applications

Abstract: The increasing number of driver assistance, infotainment and entertainment systems in automobiles results in higher requirements for bandwidth, fault tolerance and timing behaviour concerning the in-vehicle communication structure. In future, in-vehicle networks based on current technologies will reach their limits due to insufficient scalability and complexity. Real-time (RT) Ethernet is a new, scalable approach to reduce the complexity of these networks significantly.This paper demonstrates the architecture … Show more

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Cited by 23 publications
(16 citation statements)
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“…13 shows worst case VEGa latency compared with existing work in the literature, in the absence of cross traffic. As observed, our architecture outperforms gateway structures based on software-based approaches (Lim et al [23] {simulation results}, Kim et al [20], Yang et al [18], and Müller et al [22]) and FPGA-based gateways for traditional networks (Sander et al [5]). The proposed architecture also provides over 300× lower latency (priority mode, 8-byte message) than automotive-grade microcontroller-based gateways between traditional networks (LIN, CAN, and Atacama [7] Inter-domain Priority [23] Inter-domain Priority [20] FlexRay-CAN [18] Time-triggered [22] Latency (µs) Fig.…”
Section: Evaluating Vegasupporting
confidence: 59%
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“…13 shows worst case VEGa latency compared with existing work in the literature, in the absence of cross traffic. As observed, our architecture outperforms gateway structures based on software-based approaches (Lim et al [23] {simulation results}, Kim et al [20], Yang et al [18], and Müller et al [22]) and FPGA-based gateways for traditional networks (Sander et al [5]). The proposed architecture also provides over 300× lower latency (priority mode, 8-byte message) than automotive-grade microcontroller-based gateways between traditional networks (LIN, CAN, and Atacama [7] Inter-domain Priority [23] Inter-domain Priority [20] FlexRay-CAN [18] Time-triggered [22] Latency (µs) Fig.…”
Section: Evaluating Vegasupporting
confidence: 59%
“…Many papers describe gateway architectures without reporting key performance parameters like end-to-end latency measured through experiments. Processor-based gateway architectures that incorporate Ethernet have also been discussed in the literature [20], [21], [22]. Evaluations show that this approach cannot provide reliable and efficient switching at full throughput with large payload sizes.…”
Section: Introductionmentioning
confidence: 99%
“…Compared with the precision of the software implementation (approx. 1 μs jitter) implemented in previous work [7], the timing accuracy could be improved by 10 times with the hardware co-processor. …”
Section: A Time-triggered Transmissionmentioning
confidence: 99%
“…In previous work, the challenges of a pure software stack for time-triggered communication on microcontrollers was shown [7]. The implementation based on a system-on-chip (SoC) design with hardware timestamping uses a fixed-point timer with a resolution of 10 ns for the scheduling.…”
Section: Previous and Related Workmentioning
confidence: 99%
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