A Real-Time Occlusion Aware Hardware Structure for Disparity Map Computation

Abstract

Abstract. Many machine vision applications deal with depth estimation in a scene. Disparity map recovery from a stereo image pair has been extensively studied by the computer vision community. Previous methods are mainly restricted to software based techniques on general-purpose architectures, presenting relatively high execution time due to the computationally complex algorithms involved. In this paper a new hardware module suitable for real-time disparity map computation module is realized. This enables a hardware based occlusion-aware parallel-pipelined design, implemented on a single FPGA device with a typical operating frequency of 511 MHz. It provides accurate disparity map computation at a rate of 768 frames per second, given a stereo image pair with a disparity range of 80 pixels and 640x480 pixel spatial resolution. The proposed method allows a fast disparity map computational module to be built, enabling a suitable module for real-time stereo vision applications.

Dynamically adaptive real-time disparity estimation hardware using iterative refinement

“…The hardware in [15] needs to access external memory at least five times for each pixel. The hardware presented in [19] requires external memory accesses at least seven times for each pixel assuming that the entire data allocation scheme is explained. Our proposed memory organization and data allocation scheme require reading each pixel only one time from the external memory during the search process.…”

“…The proposed dynamic reconfigurability provides better DE results than existing real-time DE hardware implementations for HR images [19][20][21] for the tested HR benchmarks. The proposed hardware architectures for AWDE and AWDE-IR provides 60 frames per second at a 1024 Â 768 XGA video resolution for 128 pixel disparity range.…”

“…Various hardware architectures that are presented in literature provide real-time DE [15][16][17][18][19][20][21]. Some implemented hardware architectures only target CIF or VGA video [15][16][17][18].…”

“…The systems proposed in [19][20][21] claim to reach real-time for HR video. Still, their quality results in terms of the HR benchmarks given in [11] are not provided.…”

“…Still, their quality results in terms of the HR benchmarks given in [11] are not provided. Authors [19] claims to reach 550 fps for 80 pixel disparity range at a 800 Â 600 video resolution, but it requires extremely large hardware resources. A simple edgedirected method presented in [20] reaches 50 fps at a 1280 Â 1024 video resolution and 120 pixel disparity range, but does not provide satisfactory DE results due to a low-complexity architecture.…”