A Real Time Simulator of a Phase Shifted Converter for High Frequency Applications

Gherman, Tudor; Petreuş, Dorin; Cirstea, Marcian

doi:10.4316/aece.2020.03002

Cited by 3 publications

(5 citation statements)

References 16 publications

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“…The proposed methodology is compared to existing ones, given in refs. [9][10][11][12]. The de-facto choice for target technology is the FPGA.…”

Section: Resultsmentioning

confidence: 99%

“…The asynchronous buck converter model was implemented in a previous work [2]; thus, only a brief review is given in this section. The buck converter model is depicted in Figure 6, alongside the iterative process to solve its ODE system in Equation (9). In the previous section (synchronous buck), the low side switch was modeled a ideal switch.…”

Section: Ideal Asynchronous Buckmentioning

confidence: 99%

“…Ref. [9] deals with the RTS of a phase shifter converter for high frequency applications. It demonstrates the necessity of a small simulation step-less than 20 ns for a 200 kHz SMPSfor avoiding false limit cycling behavior and obtaining an accurate closed loop response by the RTS.…”

Section: Introductionmentioning

confidence: 99%

“…This situation is solved in [11] by applying a predictor/corrector numerical integration method (a combination of forward and backward Euler solver). The aforementioned emulators [9][10][11] are, in essence, custom, low-cost solutions. Professional tools are also available, such as eFPGASIM [12], a powerful and intuitive FPGA-based emulator.…”

Section: Introductionmentioning

confidence: 99%

“…Our solution is compared with existing ones, given in refs. [9][10][11][12]; • A digital proportional-integrative-derivative (PID) controller design method was devised using emulated hardware (real-time simulation). The hardware emulation allows the designer to manually tune the PID controller coefficients, without any harm to the actual power stage.…”

mentioning

confidence: 99%

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Hardware Emulation of Step-Down Converter Power Stages for Digital Control Design

et al. 2023

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This paper proposes a methodology of delivering the emulation hardware of several step-down converter power stages. The generalized emulator design methodology follows these steps: first, the power stage is described using an ordinary differential equation system; second, the ordinary differential equation system is solved using Euler’s method, and thus an accurate time-domain model is obtained; next, this time-domain model can be described using either general-purpose programming language (MATLAB, C, etc.) or hardware description language (VHDL, Verilog, etc.). As a result, the emulator has been created; validation of the emulator may be carried out by comparing it to SPICE transient simulations. Finally, the validated emulator can be implemented on the preferred target technology, either in a general-purpose processor or a field programmable gate array. As the emulator relies on the ordinary differential equation system of the power stage, it has better behavioral accuracy than the emulators based on average state space models. Moreover, this paper also presents the design methodology of a manually tuned proportional–integrative–derivative controller deployed on a field programmable gate array.

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“…The proposed methodology is compared to existing ones, given in refs. [9][10][11][12]. The de-facto choice for target technology is the FPGA.…”

Section: Resultsmentioning

confidence: 99%

Section: Ideal Asynchronous Buckmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%