A real-time stereo vision sensor based on FPGA realization of orientation code matching

Ohmura, Isao; Mitamura, Tomoyuki; Takauji, Hidenori; Kaneko, Shun’ichi

doi:10.1109/isot.2010.5687334

Cited by 3 publications

(2 citation statements)

References 6 publications

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“…Although some work using FPGA pipelines has been published recently, all existing real-time hardware systems for video processing and disparity analysis focused on lower-resolution video streams [6][7][8][9][10][11][12]. No work has been successfully extended for high-definition video due to the super-linear increase in processing complexity.…”

Section: Related Workmentioning

confidence: 99%

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An FPGA-based processing pipeline for high-definition stereo video

Greisen

Heinzle

Groß

et al. 2011

J Image Video Proc.

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This paper presents a real-time processing platform for high-definition stereo video. The system is capable to process stereo video streams at resolutions up to 1, 920 × 1, 080 at 30 frames per second (1080p30). In the hybrid FPGA-GPU-CPU system, a high-density FPGA is used not only to perform the low-level image processing tasks such as color interpolation and cross-image color correction, but also to carry out radial undistortion, image rectification, and disparity estimation. We show how the corresponding algorithms can be implemented very efficiently in programmable hardware, relieving the GPU from the burden of these tasks. Our FPGA implementation results are compared with corresponding GPU implementations and with other implementations reported in the literature.

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