A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition

Wei, Xing; Yang, Haigang; Li, Wei; Huang, Zhihong; Yin, Tao; Yu, Le

doi:10.1016/j.vlsi.2019.02.008

Cited by 6 publications

(7 citation statements)

References 14 publications

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“…ADP values of the proposed unit are very impressive and they differ by 18% & 22% with Xing's FDP unit [12] in single & double precision implementations. It also differs by 34% & 60% with Sohn's FDP unit [18] in single & double precision implementations.…”

Section: Performance Evaluation and Resultsmentioning

confidence: 94%

“…The proposed single precision PFFDP unit consumes 45% & 15% less area when compare to that of Lang's discrete FDP unit [19] & Sohn's FDP unit [18] respectively. Although the proposed PFFDP unit consumes 6% more area when compare to that of Xing's FDP unit [12] in single precision implementation, it dominates Xing's by occupies 11% less area in double precision implementation. Xing's FDP unit [12] consumes 12% & 7% higher power consumption than the proposed PFFDP unit in single and double precision implementations respectively.…”

Section: Performance Evaluation and Resultsmentioning

confidence: 95%

“…Although the proposed PFFDP unit consumes 6% more area when compare to that of Xing's FDP unit [12] in single precision implementation, it dominates Xing's by occupies 11% less area in double precision implementation. Xing's FDP unit [12] consumes 12% & 7% higher power consumption than the proposed PFFDP unit in single and double precision implementations respectively. It also beats rest of the FDP units with significant margin.…”

Section: Performance Evaluation and Resultsmentioning

confidence: 95%

“…It also differs by 34% & 60% with Sohn's FDP unit [18] in single & double precision implementations. The other important parameter PDP values are also compared with Xing's FDP unit [12] that differs by 27% & 18% in single & double precision implementations. Lower ADP & PDP values the more balanced system performance.…”

Section: Performance Evaluation and Resultsmentioning

confidence: 99%

“…Figure 1 shows enhanced version of traditional FDP [12] with four stage pipeline concept, where the focus is on parallel multiplier and PFCF-CLA adder. The remaining stages are alignment, 2's compliment, leading zero anticipatory(LZA) and finally rounding & normalization operations.…”

Section: Proposed Architecturesmentioning

confidence: 99%

See 4 more Smart Citations

Area and Power Efficient Fused Floating-point Dot Product Unit based on Radix-2r Multiplier & Pipeline Feedforward-Cutset-Free Carry-Lookahead Adder

Babu¹

2021

ITII

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Fused floating point operations play a major role in many DSP applications to reduce operational area & power consumption. Radix-2r multiplier (using 7-bit encoder technique) & pipeline feedforward-cutset-free carry-lookahead adder(PFCF-CLA) are used to enhance the traditional FDP unit. Pipeline concept is also infused into system to get the desired pipeline fused floating-point dot product (PFFDP) operations. Synthesis results are obtained using 60nm standard library with 1GHz clock. Power consumption of single & double precision operations are 2.24mW & 3.67mW respectively. The die areas are 27.48 mm2 , 46.72mm2 with an execution time of 1.91 ns , 2.07 ns for a single & double precision operations respectively. Comparison with previous data has also been performed. The area-delay product(ADP) & power-delay product(PDP) of our proposed architecture are 18%,22% & 27%,18% for single and double precision operations respectively.

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Section: Performance Evaluation and Resultsmentioning

confidence: 94%

Section: Performance Evaluation and Resultsmentioning

confidence: 95%

Section: Performance Evaluation and Resultsmentioning

confidence: 95%

Section: Performance Evaluation and Resultsmentioning

confidence: 99%

Section: Proposed Architecturesmentioning

confidence: 99%

See 3 more Smart Citations

Area and Power Efficient Fused Floating-point Dot Product Unit based on Radix-2r Multiplier & Pipeline Feedforward-Cutset-Free Carry-Lookahead Adder

Babu¹

2021

ITII

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Design of the vector floating-point unit with high area efficiency

Lai

2023

J. Phys.: Conf. Ser.

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With the development of the information age, there is an increasing trend towards mixed precision and vector operations in floating point arithmetic. Traditional floating-point arithmetic is usually implemented using multiple modules to ensure the required speed. Still, this approach significantly increases area and reduces area efficiency, resulting in the wastage of hardware resources. This paper focuses on optimizing speed and area to improve the area’s efficiency. The proposed floating-point unit designed can perform half-precision, single-precision, and double-precision floating-point operations. Under the TSMC 7 nm process, its maximum operating frequency is increased by 5%–37%, the area is reduced by 33%–58%, and area efficiency is increased by 63%–144%.

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Design of Dynamic NOC based Multi-core Floating Point processing element FFT for VLSI Architecture

Sivaprakasam,

Esakki Rajavel,

Chinnasamy

et al. 2023

2023 International Conference on Emerging Research in Computational Science (ICERCS)

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A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition

Cited by 6 publications

References 14 publications

Area and Power Efficient Fused Floating-point Dot Product Unit based on Radix-2r Multiplier & Pipeline Feedforward-Cutset-Free Carry-Lookahead Adder

Area and Power Efficient Fused Floating-point Dot Product Unit based on Radix-2r Multiplier & Pipeline Feedforward-Cutset-Free Carry-Lookahead Adder

Design of the vector floating-point unit with high area efficiency

Design of Dynamic NOC based Multi-core Floating Point processing element FFT for VLSI Architecture

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